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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 352

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 38 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.57  2005/02/21 11:35:33  igorm
45
// Defer indication fixed.
46
//
47 329 igorm
// Revision 1.56  2004/04/30 10:30:00  igorm
48
// Accidently deleted line put back.
49
//
50 323 igorm
// Revision 1.55  2004/04/26 15:26:23  igorm
51
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
52
//   previous update of the core.
53
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
54
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
55
//   register. (thanks to Mathias and Torbjorn)
56
// - Multicast reception was fixed. Thanks to Ulrich Gries
57
//
58 321 igorm
// Revision 1.54  2003/11/12 18:24:59  tadejm
59
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
60
//
61 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
62
// mbist signals updated according to newest convention
63
//
64 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
65
// Reset has priority in some flipflops.
66
//
67 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
68
// A new bug (entered with previous update) fixed. When abort occured sometimes
69
// data transmission was blocked.
70
//
71 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
79
// When in full duplex, transmit was sometimes blocked. Fixed.
80
//
81 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
82
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
83
// anywhere. Removed.
84
//
85 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
86
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
87
// synchronized.
88
//
89 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
90
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
91
// that a frame was received because of the promiscous mode.
92
//
93 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
94
// RxError is not generated when small frame reception is enabled and small
95
// frames are received.
96
//
97 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
98
// case changed to casex.
99
//
100 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
101
// Changed BIST scan signals.
102
//
103 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
104
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
105
//
106 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
107
// TxStatus is written after last access to the TX fifo is finished (in case of abort
108
// or retry). TxDone is fixed.
109
//
110 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
111
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
112
// TxDone and TxRetry are generated after the current WISHBONE access is
113
// finished.
114
//
115 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
116
// BIST added.
117
//
118 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
119
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
120
//
121 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
122
// Reception is possible after RxPointer is read and not after BD is read. For
123
// that reason RxBDReady is changed to RxReady.
124
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
125
// comes, interrupt is generated.
126
//
127 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
128
// Ethernet debug registers removed.
129
//
130 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
131
// Async reset for WB_ACK_O removed (when core was in reset, it was
132
// impossible to access BDs).
133
// RxPointers and TxPointers names changed to be more descriptive.
134
// TxUnderRun synchronized.
135
//
136 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
137
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
138
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
139
// was not used OK.
140
//
141 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
142
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
143
// need to multiply or devide any more.
144
//
145 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
146
// WriteRxDataToMemory signal changed so end of frame (when last word is
147
// written to fifo) is changed.
148
//
149 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
150
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
151
//
152 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
153
// ShiftEnded synchronization changed.
154
//
155 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
156
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
157
//
158 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
159
// RxPointer bug fixed.
160
//
161 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
162
// Previous bug wasn't succesfully removed. Now fixed.
163
//
164 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
165
// Master state machine had a bug when switching from master write to
166
// master read.
167
//
168 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
169
// m_wb_cyc_o signal released after every single transfer.
170
//
171 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
172
// Outputs registered. Reset changed for eth_wishbone module.
173
//
174 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
175
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
176
// bug fixed.
177
//
178 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
179
// Small typo fixed.
180
//
181 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
182
// Any address can be used for Tx and Rx BD pointers. Address does not need
183
// to be aligned.
184
//
185 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
186
// Comments in Slovene language removed.
187
//
188 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
189
// casex changed with case, fifo reset changed.
190
//
191 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
192
// rx_fifo was not always cleared ok. Fixed.
193
//
194 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
195
// Status was not latched correctly sometimes. Fixed.
196
//
197 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
198
// Big Endian problem when sending frames fixed.
199
//
200 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
201
// Byte ordering changed (Big Endian used). casex changed with case because
202
// Xilinx Foundation had problems. Tested in HW. It WORKS.
203
//
204 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
205
// Small fixes for external/internal DMA missmatches.
206
//
207 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
208
// Interrupts changed
209
//
210 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
211
// Status was not written correctly when frames were discarted because of
212
// address mismatch.
213
//
214 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
215
// RxStartFrm cleared when abort or retry comes.
216
//
217 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
218
// Changes that were lost when updating from 1.5 to 1.8 fixed.
219
//
220 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
221
// Addition  of new module eth_addrcheck.v
222
//
223
// Revision 1.7  2002/02/12 17:03:47  mohor
224
// RxOverRun added to statuses.
225
//
226
// Revision 1.6  2002/02/11 09:18:22  mohor
227
// Tx status is written back to the BD.
228
//
229 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
230
// Rx status is written back to the BD.
231
//
232 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
233
// non-DMA host interface added. Select the right configutation in eth_defines.
234
//
235 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
236
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
237
// MHz. Statuses, overrun, control frame transmission and reception still  need
238
// to be fixed.
239
//
240 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
241
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
242
// added.
243
//
244 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
245
// Initial version. Equals to eth_wishbonedma.v at this moment.
246 38 mohor
//
247
//
248
//
249
 
250
`include "eth_defines.v"
251
`include "timescale.v"
252
 
253
 
254
module eth_wishbone
255
   (
256
 
257
    // WISHBONE common
258 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
259 38 mohor
 
260
    // WISHBONE slave
261 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
262 40 mohor
    BDCs,
263 38 mohor
 
264 40 mohor
    Reset,
265
 
266 39 mohor
    // WISHBONE master
267
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
268
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
269
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
270
 
271 219 mohor
`ifdef ETH_WISHBONE_B3
272
    m_wb_cti_o, m_wb_bte_o,
273
`endif
274
 
275 38 mohor
    //TX
276 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
277 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
278 38 mohor
    PerPacketPad,
279
 
280
    //RX
281 272 tadejm
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
282 38 mohor
 
283
    // Register
284 321 igorm
    r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
285 38 mohor
 
286
    // Interrupts
287 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
288 42 mohor
 
289 60 mohor
    // Rx Status
290 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
291 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
292 261 mohor
    ReceivedPauseFrm,
293 60 mohor
 
294
    // Tx Status
295 329 igorm
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
296 164 mohor
 
297 210 mohor
    // Bist
298
`ifdef ETH_BIST
299 227 tadejm
    ,
300
    // debug chain signals
301 302 markom
    mbist_si_i,       // bist scan serial in
302
    mbist_so_o,       // bist scan serial out
303
    mbist_ctrl_i        // bist chain shift control
304 210 mohor
`endif
305
 
306
 
307
 
308 38 mohor
                );
309
 
310
 
311 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
312
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
313
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
314
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
315
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
316
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
317 38 mohor
 
318 150 mohor
 
319 38 mohor
// WISHBONE common
320
input           WB_CLK_I;       // WISHBONE clock
321
input  [31:0]   WB_DAT_I;       // WISHBONE data input
322
output [31:0]   WB_DAT_O;       // WISHBONE data output
323
 
324
// WISHBONE slave
325
input   [9:2]   WB_ADR_I;       // WISHBONE address input
326
input           WB_WE_I;        // WISHBONE write enable input
327 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
328 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
329
 
330 39 mohor
// WISHBONE master
331 329 igorm
output  [29:0]  m_wb_adr_o;     // 
332 39 mohor
output   [3:0]  m_wb_sel_o;     // 
333
output          m_wb_we_o;      // 
334
output  [31:0]  m_wb_dat_o;     // 
335
output          m_wb_cyc_o;     // 
336
output          m_wb_stb_o;     // 
337
input   [31:0]  m_wb_dat_i;     // 
338
input           m_wb_ack_i;     // 
339
input           m_wb_err_i;     // 
340
 
341 219 mohor
`ifdef ETH_WISHBONE_B3
342
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
343
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
344
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
345
`endif
346
 
347 40 mohor
input           Reset;       // Reset signal
348 39 mohor
 
349 60 mohor
// Rx Status signals
350 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
351
input           LatchedCrcError;  // CRC error
352
input           RxLateCollision;  // Late collision occured while receiving frame
353
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
354
input           DribbleNibble;    // Extra nibble received
355
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
356
input    [15:0] RxLength;         // Length of the incoming frame
357
input           LoadRxStatus;     // Rx status was loaded
358 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
359 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
360 261 mohor
input           r_RxFlow;
361 270 mohor
input           r_PassAll;
362 261 mohor
input           ReceivedPauseFrm;
363 39 mohor
 
364 60 mohor
// Tx Status signals
365
input     [3:0] RetryCntLatched;  // Latched Retry Counter
366
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
367
input           LateCollLatched;  // Late collision occured
368
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
369 329 igorm
output          RstDeferLatched;
370 60 mohor
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
371
 
372 38 mohor
// Tx
373
input           MTxClk;         // Transmit clock (from PHY)
374
input           TxUsedData;     // Transmit packet used data
375
input           TxRetry;        // Transmit packet retry
376
input           TxAbort;        // Transmit packet abort
377
input           TxDone;         // Transmission ended
378
output          TxStartFrm;     // Transmit packet start frame
379
output          TxEndFrm;       // Transmit packet end frame
380
output  [7:0]   TxData;         // Transmit packet data byte
381
output          TxUnderRun;     // Transmit packet under-run
382
output          PerPacketCrcEn; // Per packet crc enable
383
output          PerPacketPad;   // Per packet pading
384
 
385
// Rx
386
input           MRxClk;         // Receive clock (from PHY)
387
input   [7:0]   RxData;         // Received data byte (from PHY)
388
input           RxValid;        // 
389
input           RxStartFrm;     // 
390
input           RxEndFrm;       // 
391 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
392 272 tadejm
output          RxStatusWriteLatched_sync2;
393 38 mohor
 
394
//Register
395
input           r_TxEn;         // Transmit enable
396
input           r_RxEn;         // Receive enable
397
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
398
 
399
// Interrupts
400
output TxB_IRQ;
401
output TxE_IRQ;
402
output RxB_IRQ;
403 77 mohor
output RxE_IRQ;
404 38 mohor
output Busy_IRQ;
405
 
406 77 mohor
 
407 210 mohor
// Bist
408
`ifdef ETH_BIST
409 302 markom
input   mbist_si_i;       // bist scan serial in
410
output  mbist_so_o;       // bist scan serial out
411
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
412 210 mohor
`endif
413
 
414 77 mohor
reg TxB_IRQ;
415
reg TxE_IRQ;
416
reg RxB_IRQ;
417
reg RxE_IRQ;
418
 
419 38 mohor
reg             TxStartFrm;
420
reg             TxEndFrm;
421
reg     [7:0]   TxData;
422
 
423
reg             TxUnderRun;
424 60 mohor
reg             TxUnderRun_wb;
425 38 mohor
 
426
reg             TxBDRead;
427 39 mohor
wire            TxStatusWrite;
428 38 mohor
 
429
reg     [1:0]   TxValidBytesLatched;
430
 
431
reg    [15:0]   TxLength;
432 60 mohor
reg    [15:0]   LatchedTxLength;
433
reg   [14:11]   TxStatus;
434 38 mohor
 
435 60 mohor
reg   [14:13]   RxStatus;
436 38 mohor
 
437
reg             TxStartFrm_wb;
438
reg             TxRetry_wb;
439 39 mohor
reg             TxAbort_wb;
440 38 mohor
reg             TxDone_wb;
441
 
442
reg             TxDone_wb_q;
443
reg             TxAbort_wb_q;
444 39 mohor
reg             TxRetry_wb_q;
445 219 mohor
reg             TxRetryPacket;
446 221 mohor
reg             TxRetryPacket_NotCleared;
447
reg             TxDonePacket;
448
reg             TxDonePacket_NotCleared;
449 219 mohor
reg             TxAbortPacket;
450 221 mohor
reg             TxAbortPacket_NotCleared;
451 38 mohor
reg             RxBDReady;
452 166 mohor
reg             RxReady;
453 38 mohor
reg             TxBDReady;
454
 
455
reg             RxBDRead;
456
 
457
reg    [31:0]   TxDataLatched;
458
reg     [1:0]   TxByteCnt;
459
reg             LastWord;
460 39 mohor
reg             ReadTxDataFromFifo_tck;
461 38 mohor
 
462
reg             BlockingTxStatusWrite;
463
reg             BlockingTxBDRead;
464
 
465 40 mohor
reg             Flop;
466 38 mohor
 
467 329 igorm
reg     [7:1]   TxBDAddress;
468
reg     [7:1]   RxBDAddress;
469 38 mohor
 
470
reg             TxRetrySync1;
471
reg             TxAbortSync1;
472 39 mohor
reg             TxDoneSync1;
473 38 mohor
 
474
reg             TxAbort_q;
475
reg             TxRetry_q;
476
reg             TxUsedData_q;
477
 
478
reg    [31:0]   RxDataLatched2;
479 82 mohor
 
480
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
481
 
482 38 mohor
reg     [1:0]   RxValidBytes;
483
reg     [1:0]   RxByteCnt;
484
reg             LastByteIn;
485
reg             ShiftWillEnd;
486
 
487 40 mohor
reg             WriteRxDataToFifo;
488 42 mohor
reg    [15:0]   LatchedRxLength;
489 64 mohor
reg             RxAbortLatched;
490 38 mohor
 
491 40 mohor
reg             ShiftEnded;
492 60 mohor
reg             RxOverrun;
493 38 mohor
 
494 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
495 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
496 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
497
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
498 38 mohor
 
499 39 mohor
reg             TxEndFrm_wb;
500 38 mohor
 
501 39 mohor
wire            TxRetryPulse;
502 38 mohor
wire            TxDonePulse;
503
wire            TxAbortPulse;
504
 
505
wire            StartRxBDRead;
506
 
507
wire            StartTxBDRead;
508
 
509
wire            TxIRQEn;
510
wire            WrapTxStatusBit;
511
 
512 77 mohor
wire            RxIRQEn;
513 38 mohor
wire            WrapRxStatusBit;
514
 
515
wire    [1:0]   TxValidBytes;
516
 
517 329 igorm
wire    [7:1]   TempTxBDAddress;
518
wire    [7:1]   TempRxBDAddress;
519 38 mohor
 
520 272 tadejm
wire            RxStatusWrite;
521 329 igorm
wire            RxBufferFull;
522
wire            RxBufferAlmostEmpty;
523
wire            RxBufferEmpty;
524 272 tadejm
 
525 106 mohor
reg             WB_ACK_O;
526 38 mohor
 
527 261 mohor
wire    [8:0]   RxStatusIn;
528
reg     [8:0]   RxStatusInLatched;
529 42 mohor
 
530 39 mohor
reg WbEn, WbEn_q;
531
reg RxEn, RxEn_q;
532
reg TxEn, TxEn_q;
533 321 igorm
reg r_TxEn_q;
534
reg r_RxEn_q;
535 38 mohor
 
536 39 mohor
wire ram_ce;
537 304 tadejm
wire [3:0]  ram_we;
538 39 mohor
wire ram_oe;
539
reg [7:0]   ram_addr;
540
reg [31:0]  ram_di;
541
wire [31:0] ram_do;
542 38 mohor
 
543 39 mohor
wire StartTxPointerRead;
544
reg  TxPointerRead;
545
reg TxEn_needed;
546 40 mohor
reg RxEn_needed;
547 38 mohor
 
548 40 mohor
wire StartRxPointerRead;
549
reg RxPointerRead;
550 38 mohor
 
551 219 mohor
`ifdef ETH_WISHBONE_B3
552
assign m_wb_bte_o = 2'b00;    // Linear burst
553
`endif
554 39 mohor
 
555 329 igorm
assign m_wb_stb_o = m_wb_cyc_o;
556 219 mohor
 
557 159 mohor
always @ (posedge WB_CLK_I)
558 40 mohor
begin
559 352 olof
  WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
560 40 mohor
end
561 39 mohor
 
562 106 mohor
assign WB_DAT_O = ram_do;
563 39 mohor
 
564 41 mohor
// Generic synchronous single-port RAM interface
565 119 mohor
eth_spram_256x32 bd_ram (
566 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
567 210 mohor
`ifdef ETH_BIST
568 227 tadejm
  ,
569 302 markom
  .mbist_si_i       (mbist_si_i),
570
  .mbist_so_o       (mbist_so_o),
571
  .mbist_ctrl_i       (mbist_ctrl_i)
572 210 mohor
`endif
573 39 mohor
);
574 41 mohor
 
575 39 mohor
assign ram_ce = 1'b1;
576 304 tadejm
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
577 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
578 39 mohor
 
579
 
580 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
581 38 mohor
begin
582 40 mohor
  if(Reset)
583 352 olof
    TxEn_needed <= 1'b0;
584 38 mohor
  else
585 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
586 352 olof
    TxEn_needed <= 1'b1;
587 39 mohor
  else
588
  if(TxPointerRead & TxEn & TxEn_q)
589 352 olof
    TxEn_needed <= 1'b0;
590 38 mohor
end
591
 
592 39 mohor
// Enabling access to the RAM for three devices.
593 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
594 39 mohor
begin
595 40 mohor
  if(Reset)
596 39 mohor
    begin
597 352 olof
      WbEn <= 1'b1;
598
      RxEn <= 1'b0;
599
      TxEn <= 1'b0;
600
      ram_addr <= 8'h0;
601
      ram_di <= 32'h0;
602
      BDRead <= 1'b0;
603
      BDWrite <= 1'b0;
604 39 mohor
    end
605
  else
606
    begin
607
      // Switching between three stages depends on enable signals
608 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
609
        5'b100_10, 5'b100_11 :
610 39 mohor
          begin
611 352 olof
            WbEn <= 1'b0;
612
            RxEn <= 1'b1;  // wb access stage and r_RxEn is enabled
613
            TxEn <= 1'b0;
614
            ram_addr <= {RxBDAddress, RxPointerRead};
615
            ram_di <= RxBDDataIn;
616 39 mohor
          end
617
        5'b100_01 :
618
          begin
619 352 olof
            WbEn <= 1'b0;
620
            RxEn <= 1'b0;
621
            TxEn <= 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
622
            ram_addr <= {TxBDAddress, TxPointerRead};
623
            ram_di <= TxBDDataIn;
624 39 mohor
          end
625 90 mohor
        5'b010_00, 5'b010_10 :
626 39 mohor
          begin
627 352 olof
            WbEn <= 1'b1;  // RxEn access stage and r_TxEn is disabled
628
            RxEn <= 1'b0;
629
            TxEn <= 1'b0;
630
            ram_addr <= WB_ADR_I[9:2];
631
            ram_di <= WB_DAT_I;
632
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
633
            BDRead <= (|BDCs) & ~WB_WE_I;
634 39 mohor
          end
635 90 mohor
        5'b010_01, 5'b010_11 :
636 39 mohor
          begin
637 352 olof
            WbEn <= 1'b0;
638
            RxEn <= 1'b0;
639
            TxEn <= 1'b1;  // RxEn access stage and r_TxEn is enabled
640
            ram_addr <= {TxBDAddress, TxPointerRead};
641
            ram_di <= TxBDDataIn;
642 39 mohor
          end
643 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
644 39 mohor
          begin
645 352 olof
            WbEn <= 1'b1;  // TxEn access stage (we always go to wb access stage)
646
            RxEn <= 1'b0;
647
            TxEn <= 1'b0;
648
            ram_addr <= WB_ADR_I[9:2];
649
            ram_di <= WB_DAT_I;
650
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
651
            BDRead <= (|BDCs) & ~WB_WE_I;
652 39 mohor
          end
653
        5'b100_00 :
654
          begin
655 352 olof
            WbEn <= 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
656 39 mohor
          end
657
        5'b000_00 :
658
          begin
659 352 olof
            WbEn <= 1'b1;  // Idle state. We go to WbEn access stage.
660
            RxEn <= 1'b0;
661
            TxEn <= 1'b0;
662
            ram_addr <= WB_ADR_I[9:2];
663
            ram_di <= WB_DAT_I;
664
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
665
            BDRead <= (|BDCs) & ~WB_WE_I;
666 39 mohor
          end
667
      endcase
668
    end
669
end
670
 
671
 
672
// Delayed stage signals
673 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
674 39 mohor
begin
675 40 mohor
  if(Reset)
676 39 mohor
    begin
677 352 olof
      WbEn_q <= 1'b0;
678
      RxEn_q <= 1'b0;
679
      TxEn_q <= 1'b0;
680
      r_TxEn_q <= 1'b0;
681
      r_RxEn_q <= 1'b0;
682 39 mohor
    end
683
  else
684
    begin
685 352 olof
      WbEn_q <= WbEn;
686
      RxEn_q <= RxEn;
687
      TxEn_q <= TxEn;
688
      r_TxEn_q <= r_TxEn;
689
      r_RxEn_q <= r_RxEn;
690 39 mohor
    end
691
end
692
 
693 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
694 40 mohor
always @ (posedge MTxClk or posedge Reset)
695 38 mohor
begin
696 40 mohor
  if(Reset)
697 352 olof
    Flop <= 1'b0;
698 38 mohor
  else
699
  if(TxDone | TxAbort | TxRetry_q)
700 352 olof
    Flop <= 1'b0;
701 38 mohor
  else
702
  if(TxUsedData)
703 352 olof
    Flop <= ~Flop;
704 38 mohor
end
705
 
706 39 mohor
wire ResetTxBDReady;
707
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
708 38 mohor
 
709
// Latching READY status of the Tx buffer descriptor
710 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
711 38 mohor
begin
712 40 mohor
  if(Reset)
713 352 olof
    TxBDReady <= 1'b0;
714 38 mohor
  else
715 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
716 352 olof
    TxBDReady <= ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
717 40 mohor
  else                                                // Only packets larger then 4 bytes are transmitted.
718 39 mohor
  if(ResetTxBDReady)
719 352 olof
    TxBDReady <= 1'b0;
720 38 mohor
end
721
 
722
 
723 39 mohor
// Reading the Tx buffer descriptor
724 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
725 39 mohor
 
726 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
727 38 mohor
begin
728 40 mohor
  if(Reset)
729 352 olof
    TxBDRead <= 1'b1;
730 38 mohor
  else
731 110 mohor
  if(StartTxBDRead)
732 352 olof
    TxBDRead <= 1'b1;
733 38 mohor
  else
734 39 mohor
  if(TxBDReady)
735 352 olof
    TxBDRead <= 1'b0;
736 38 mohor
end
737
 
738
 
739 39 mohor
// Reading Tx BD pointer
740
assign StartTxPointerRead = TxBDRead & TxBDReady;
741 38 mohor
 
742 39 mohor
// Reading Tx BD Pointer
743 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
744 38 mohor
begin
745 40 mohor
  if(Reset)
746 352 olof
    TxPointerRead <= 1'b0;
747 38 mohor
  else
748 39 mohor
  if(StartTxPointerRead)
749 352 olof
    TxPointerRead <= 1'b1;
750 38 mohor
  else
751 39 mohor
  if(TxEn_q)
752 352 olof
    TxPointerRead <= 1'b0;
753 38 mohor
end
754
 
755
 
756 39 mohor
// Writing status back to the Tx buffer descriptor
757 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
758 38 mohor
 
759
 
760
 
761 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
762 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
763 38 mohor
begin
764 40 mohor
  if(Reset)
765 352 olof
    BlockingTxStatusWrite <= 1'b0;
766 38 mohor
  else
767 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
768 352 olof
    BlockingTxStatusWrite <= 1'b0;
769 272 tadejm
  else
770 39 mohor
  if(TxStatusWrite)
771 352 olof
    BlockingTxStatusWrite <= 1'b1;
772 38 mohor
end
773
 
774
 
775 159 mohor
reg BlockingTxStatusWrite_sync1;
776
reg BlockingTxStatusWrite_sync2;
777 329 igorm
reg BlockingTxStatusWrite_sync3;
778 159 mohor
 
779
// Synchronizing BlockingTxStatusWrite to MTxClk
780
always @ (posedge MTxClk or posedge Reset)
781
begin
782
  if(Reset)
783 352 olof
    BlockingTxStatusWrite_sync1 <= 1'b0;
784 159 mohor
  else
785 352 olof
    BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
786 159 mohor
end
787
 
788
// Synchronizing BlockingTxStatusWrite to MTxClk
789
always @ (posedge MTxClk or posedge Reset)
790
begin
791
  if(Reset)
792 352 olof
    BlockingTxStatusWrite_sync2 <= 1'b0;
793 159 mohor
  else
794 352 olof
    BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
795 159 mohor
end
796
 
797 329 igorm
// Synchronizing BlockingTxStatusWrite to MTxClk
798
always @ (posedge MTxClk or posedge Reset)
799
begin
800
  if(Reset)
801 352 olof
    BlockingTxStatusWrite_sync3 <= 1'b0;
802 329 igorm
  else
803 352 olof
    BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
804 329 igorm
end
805 159 mohor
 
806 329 igorm
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
807
 
808 39 mohor
// TxBDRead state is activated only once. 
809 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
810 39 mohor
begin
811 40 mohor
  if(Reset)
812 352 olof
    BlockingTxBDRead <= 1'b0;
813 39 mohor
  else
814 110 mohor
  if(StartTxBDRead)
815 352 olof
    BlockingTxBDRead <= 1'b1;
816 39 mohor
  else
817 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
818 352 olof
    BlockingTxBDRead <= 1'b0;
819 39 mohor
end
820 38 mohor
 
821
 
822 39 mohor
// Latching status from the tx buffer descriptor
823
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
824 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
825 38 mohor
begin
826 40 mohor
  if(Reset)
827 352 olof
    TxStatus <= 4'h0;
828 38 mohor
  else
829 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
830 352 olof
    TxStatus <= ram_do[14:11];
831 38 mohor
end
832
 
833 40 mohor
reg ReadTxDataFromMemory;
834
wire WriteRxDataToMemory;
835 38 mohor
 
836 39 mohor
reg MasterWbTX;
837
reg MasterWbRX;
838
 
839 329 igorm
reg [29:0] m_wb_adr_o;
840 39 mohor
reg        m_wb_cyc_o;
841 96 mohor
reg  [3:0] m_wb_sel_o;
842 39 mohor
reg        m_wb_we_o;
843 40 mohor
 
844 39 mohor
wire TxLengthEq0;
845
wire TxLengthLt4;
846
 
847 150 mohor
reg BlockingIncrementTxPointer;
848 159 mohor
reg [31:2] TxPointerMSB;
849
reg [1:0]  TxPointerLSB;
850
reg [1:0]  TxPointerLSB_rst;
851
reg [31:2] RxPointerMSB;
852
reg [1:0]  RxPointerLSB_rst;
853 39 mohor
 
854 150 mohor
wire RxBurstAcc;
855
wire RxWordAcc;
856
wire RxHalfAcc;
857
wire RxByteAcc;
858
 
859 39 mohor
//Latching length from the buffer descriptor;
860 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
861 38 mohor
begin
862 40 mohor
  if(Reset)
863 352 olof
    TxLength <= 16'h0;
864 38 mohor
  else
865 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
866 352 olof
    TxLength <= ram_do[31:16];
867 38 mohor
  else
868 39 mohor
  if(MasterWbTX & m_wb_ack_i)
869
    begin
870
      if(TxLengthLt4)
871 352 olof
        TxLength <= 16'h0;
872 150 mohor
      else
873 159 mohor
      if(TxPointerLSB_rst==2'h0)
874 352 olof
        TxLength <= TxLength - 3'h4;    // Length is subtracted at the data request
875 39 mohor
      else
876 159 mohor
      if(TxPointerLSB_rst==2'h1)
877 352 olof
        TxLength <= TxLength - 3'h3;    // Length is subtracted at the data request
878 150 mohor
      else
879 159 mohor
      if(TxPointerLSB_rst==2'h2)
880 352 olof
        TxLength <= TxLength - 3'h2;    // Length is subtracted at the data request
881 150 mohor
      else
882 159 mohor
      if(TxPointerLSB_rst==2'h3)
883 352 olof
        TxLength <= TxLength - 3'h1;    // Length is subtracted at the data request
884 39 mohor
    end
885 38 mohor
end
886
 
887 96 mohor
 
888
 
889 60 mohor
//Latching length from the buffer descriptor;
890
always @ (posedge WB_CLK_I or posedge Reset)
891
begin
892
  if(Reset)
893 352 olof
    LatchedTxLength <= 16'h0;
894 60 mohor
  else
895
  if(TxEn & TxEn_q & TxBDRead)
896 352 olof
    LatchedTxLength <= ram_do[31:16];
897 60 mohor
end
898
 
899 39 mohor
assign TxLengthEq0 = TxLength == 0;
900
assign TxLengthLt4 = TxLength < 4;
901 38 mohor
 
902 150 mohor
reg cyc_cleared;
903
reg IncrTxPointer;
904 39 mohor
 
905
 
906 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
907
// because TxPointerMSB is only used for word-aligned accesses.
908 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
909 38 mohor
begin
910 40 mohor
  if(Reset)
911 352 olof
    TxPointerMSB <= 30'h0;
912 38 mohor
  else
913 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
914 352 olof
    TxPointerMSB <= ram_do[31:2];
915 38 mohor
  else
916 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
917 352 olof
    TxPointerMSB <= TxPointerMSB + 1'b1;     // TxPointer is word-aligned
918 38 mohor
end
919
 
920 96 mohor
 
921 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
922
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
923
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
924
// set by this two bits.
925 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
926
begin
927
  if(Reset)
928 352 olof
    TxPointerLSB[1:0] <= 0;
929 96 mohor
  else
930
  if(TxEn & TxEn_q & TxPointerRead)
931 352 olof
    TxPointerLSB[1:0] <= ram_do[1:0];
932 96 mohor
end
933
 
934
 
935 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
936
// After the read access, TxLength needs to be decremented for the number of the valid
937
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
938
// valid so this two bits are reset to zero. 
939 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
940
begin
941
  if(Reset)
942 352 olof
    TxPointerLSB_rst[1:0] <= 0;
943 150 mohor
  else
944
  if(TxEn & TxEn_q & TxPointerRead)
945 352 olof
    TxPointerLSB_rst[1:0] <= ram_do[1:0];
946 150 mohor
  else
947
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
948 352 olof
    TxPointerLSB_rst[1:0] <= 0;
949 150 mohor
end
950 96 mohor
 
951 150 mohor
 
952 159 mohor
reg  [3:0] RxByteSel;
953 39 mohor
wire MasterAccessFinished;
954 38 mohor
 
955 39 mohor
 
956 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
957 38 mohor
begin
958 40 mohor
  if(Reset)
959 352 olof
    BlockingIncrementTxPointer <= 0;
960 38 mohor
  else
961 39 mohor
  if(MasterAccessFinished)
962 352 olof
    BlockingIncrementTxPointer <= 0;
963 38 mohor
  else
964 150 mohor
  if(IncrTxPointer)
965 352 olof
    BlockingIncrementTxPointer <= 1'b1;
966 38 mohor
end
967
 
968
 
969 39 mohor
wire TxBufferAlmostFull;
970
wire TxBufferFull;
971
wire TxBufferEmpty;
972
wire TxBufferAlmostEmpty;
973 40 mohor
wire SetReadTxDataFromMemory;
974 39 mohor
 
975 40 mohor
reg BlockReadTxDataFromMemory;
976 39 mohor
 
977 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
978 39 mohor
 
979 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
980 38 mohor
begin
981 40 mohor
  if(Reset)
982 352 olof
    ReadTxDataFromMemory <= 1'b0;
983 38 mohor
  else
984 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
985 352 olof
    ReadTxDataFromMemory <= 1'b0;
986 39 mohor
  else
987 40 mohor
  if(SetReadTxDataFromMemory)
988 352 olof
    ReadTxDataFromMemory <= 1'b1;
989 38 mohor
end
990
 
991 226 tadejm
reg tx_burst_en;
992
reg rx_burst_en;
993 221 mohor
 
994 278 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
995 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
996 221 mohor
 
997 39 mohor
wire [31:0] TxData_wb;
998
wire ReadTxDataFromFifo_wb;
999 38 mohor
 
1000 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1001 38 mohor
begin
1002 40 mohor
  if(Reset)
1003 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1004 38 mohor
  else
1005 278 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
1006 352 olof
    BlockReadTxDataFromMemory <= 1'b1;
1007 219 mohor
  else
1008 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
1009 352 olof
    BlockReadTxDataFromMemory <= 1'b0;
1010 39 mohor
end
1011
 
1012
 
1013
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
1014 349 olof
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
1015
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
1016 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
1017
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
1018 159 mohor
 
1019 226 tadejm
wire rx_burst;
1020
wire enough_data_in_rxfifo_for_burst;
1021
wire enough_data_in_rxfifo_for_burst_plus1;
1022 229 mohor
 
1023 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
1024 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1025 39 mohor
begin
1026 40 mohor
  if(Reset)
1027 38 mohor
    begin
1028 352 olof
      MasterWbTX <= 1'b0;
1029
      MasterWbRX <= 1'b0;
1030
      m_wb_adr_o <= 30'h0;
1031
      m_wb_cyc_o <= 1'b0;
1032
      m_wb_we_o  <= 1'b0;
1033
      m_wb_sel_o <= 4'h0;
1034
      cyc_cleared<= 1'b0;
1035
      tx_burst_cnt<= 0;
1036
      rx_burst_cnt<= 0;
1037
      IncrTxPointer<= 1'b0;
1038
      tx_burst_en<= 1'b1;
1039
      rx_burst_en<= 1'b0;
1040 226 tadejm
      `ifdef ETH_WISHBONE_B3
1041 352 olof
        m_wb_cti_o <= 3'b0;
1042 226 tadejm
      `endif
1043 38 mohor
    end
1044 39 mohor
  else
1045
    begin
1046
      // Switching between two stages depends on enable signals
1047 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1048 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1049 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1050 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1051 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1052 39 mohor
          begin
1053 352 olof
            MasterWbTX <= 1'b1;  // tx burst
1054
            MasterWbRX <= 1'b0;
1055
            m_wb_cyc_o <= 1'b1;
1056
            m_wb_we_o  <= 1'b0;
1057
            m_wb_sel_o <= 4'hf;
1058
            cyc_cleared<= 1'b0;
1059
            IncrTxPointer<= 1'b1;
1060
            tx_burst_cnt <= tx_burst_cnt+3'h1;
1061 226 tadejm
            if(tx_burst_cnt==0)
1062 352 olof
              m_wb_adr_o <= TxPointerMSB;
1063 226 tadejm
            else
1064 352 olof
              m_wb_adr_o <= m_wb_adr_o+1'b1;
1065 226 tadejm
 
1066
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1067
              begin
1068 352 olof
                tx_burst_en<= 1'b0;
1069 226 tadejm
              `ifdef ETH_WISHBONE_B3
1070 352 olof
                m_wb_cti_o <= 3'b111;
1071 226 tadejm
              `endif
1072
              end
1073
            else
1074
              begin
1075
              `ifdef ETH_WISHBONE_B3
1076 352 olof
                m_wb_cti_o <= 3'b010;
1077 226 tadejm
              `endif
1078
              end
1079
          end
1080 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1081
        8'b01_x1_10_x1,             // MWB continues
1082 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1083 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1084 226 tadejm
          begin
1085 352 olof
            MasterWbTX <= 1'b0;  // rx burst
1086
            MasterWbRX <= 1'b1;
1087
            m_wb_cyc_o <= 1'b1;
1088
            m_wb_we_o  <= 1'b1;
1089
            m_wb_sel_o <= RxByteSel;
1090
            IncrTxPointer<= 1'b0;
1091
            cyc_cleared<= 1'b0;
1092
            rx_burst_cnt <= rx_burst_cnt+3'h1;
1093 226 tadejm
 
1094
            if(rx_burst_cnt==0)
1095 352 olof
              m_wb_adr_o <= RxPointerMSB;
1096 226 tadejm
            else
1097 352 olof
              m_wb_adr_o <= m_wb_adr_o+1'b1;
1098 226 tadejm
 
1099
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1100
              begin
1101 352 olof
                rx_burst_en<= 1'b0;
1102 226 tadejm
              `ifdef ETH_WISHBONE_B3
1103 352 olof
                m_wb_cti_o <= 3'b111;
1104 226 tadejm
              `endif
1105
              end
1106
            else
1107
              begin
1108
              `ifdef ETH_WISHBONE_B3
1109 352 olof
                m_wb_cti_o <= 3'b010;
1110 226 tadejm
              `endif
1111
              end
1112
          end
1113 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1114 226 tadejm
          begin
1115 352 olof
            MasterWbTX <= 1'b0;
1116
            MasterWbRX <= 1'b1;
1117
            m_wb_adr_o <= RxPointerMSB;
1118
            m_wb_cyc_o <= 1'b1;
1119
            m_wb_we_o  <= 1'b1;
1120
            m_wb_sel_o <= RxByteSel;
1121
            IncrTxPointer<= 1'b0;
1122 39 mohor
          end
1123 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1124 39 mohor
          begin
1125 352 olof
            MasterWbTX <= 1'b1;
1126
            MasterWbRX <= 1'b0;
1127
            m_wb_adr_o <= TxPointerMSB;
1128
            m_wb_cyc_o <= 1'b1;
1129
            m_wb_we_o  <= 1'b0;
1130
            m_wb_sel_o <= 4'hf;
1131
            IncrTxPointer<= 1'b1;
1132 39 mohor
          end
1133 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1134 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1135 39 mohor
          begin
1136 352 olof
            MasterWbTX <= 1'b1;
1137
            MasterWbRX <= 1'b0;
1138
            m_wb_adr_o <= TxPointerMSB;
1139
            m_wb_cyc_o <= 1'b1;
1140
            m_wb_we_o  <= 1'b0;
1141
            m_wb_sel_o <= 4'hf;
1142
            cyc_cleared<= 1'b0;
1143
            IncrTxPointer<= 1'b1;
1144 39 mohor
          end
1145 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1146 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1147 39 mohor
          begin
1148 352 olof
            MasterWbTX <= 1'b0;
1149
            MasterWbRX <= 1'b1;
1150
            m_wb_adr_o <= RxPointerMSB;
1151
            m_wb_cyc_o <= 1'b1;
1152
            m_wb_we_o  <= 1'b1;
1153
            m_wb_sel_o <= RxByteSel;
1154
            cyc_cleared<= 1'b0;
1155
            IncrTxPointer<= 1'b0;
1156 39 mohor
          end
1157 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1158 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1159 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1160 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1161 39 mohor
          begin
1162 352 olof
            m_wb_cyc_o <= 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1163
            cyc_cleared<= 1'b1;
1164
            IncrTxPointer<= 1'b0;
1165
            tx_burst_cnt<= 0;
1166
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1167
            rx_burst_cnt<= 0;
1168
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1169 226 tadejm
            `ifdef ETH_WISHBONE_B3
1170 352 olof
              m_wb_cti_o <= 3'b0;
1171 226 tadejm
            `endif
1172 110 mohor
          end
1173 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1174
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1175 110 mohor
          begin
1176 352 olof
            MasterWbTX <= 1'b0;
1177
            MasterWbRX <= 1'b0;
1178
            m_wb_cyc_o <= 1'b0;
1179
            cyc_cleared<= 1'b0;
1180
            IncrTxPointer<= 1'b0;
1181
            rx_burst_cnt<= 0;
1182
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1183 226 tadejm
            `ifdef ETH_WISHBONE_B3
1184 352 olof
              m_wb_cti_o <= 3'b0;
1185 226 tadejm
            `endif
1186 39 mohor
          end
1187 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1188 127 mohor
          begin
1189 352 olof
            tx_burst_cnt<= 0;
1190
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1191 127 mohor
          end
1192 226 tadejm
        default:                    // Don't touch
1193 82 mohor
          begin
1194 352 olof
            MasterWbTX <= MasterWbTX;
1195
            MasterWbRX <= MasterWbRX;
1196
            m_wb_cyc_o <= m_wb_cyc_o;
1197
            m_wb_sel_o <= m_wb_sel_o;
1198
            IncrTxPointer<= IncrTxPointer;
1199 82 mohor
          end
1200 39 mohor
      endcase
1201
    end
1202 38 mohor
end
1203
 
1204 110 mohor
 
1205 39 mohor
wire TxFifoClear;
1206 96 mohor
 
1207 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1208 38 mohor
 
1209 349 olof
eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1210
           .DEPTH(TX_FIFO_DEPTH),
1211 352 olof
           .CNT_WIDTH(TX_FIFO_CNT_WIDTH))
1212 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1213 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1214 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1215 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1216
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1217 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1218 96 mohor
        );
1219 39 mohor
 
1220
 
1221
reg StartOccured;
1222
reg TxStartFrm_sync1;
1223
reg TxStartFrm_sync2;
1224
reg TxStartFrm_syncb1;
1225
reg TxStartFrm_syncb2;
1226
 
1227
 
1228
 
1229
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1230 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1231 38 mohor
begin
1232 40 mohor
  if(Reset)
1233 352 olof
    TxStartFrm_wb <= 1'b0;
1234 38 mohor
  else
1235 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1236 352 olof
    TxStartFrm_wb <= 1'b1;
1237 38 mohor
  else
1238 39 mohor
  if(TxStartFrm_syncb2)
1239 352 olof
    TxStartFrm_wb <= 1'b0;
1240 38 mohor
end
1241
 
1242 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1243 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1244 38 mohor
begin
1245 40 mohor
  if(Reset)
1246 352 olof
    StartOccured <= 1'b0;
1247 38 mohor
  else
1248 39 mohor
  if(TxStartFrm_wb)
1249 352 olof
    StartOccured <= 1'b1;
1250 38 mohor
  else
1251 39 mohor
  if(ResetTxBDReady)
1252 352 olof
    StartOccured <= 1'b0;
1253 38 mohor
end
1254
 
1255 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1256 40 mohor
always @ (posedge MTxClk or posedge Reset)
1257 39 mohor
begin
1258 40 mohor
  if(Reset)
1259 352 olof
    TxStartFrm_sync1 <= 1'b0;
1260 39 mohor
  else
1261 352 olof
    TxStartFrm_sync1 <= TxStartFrm_wb;
1262 39 mohor
end
1263 38 mohor
 
1264 40 mohor
always @ (posedge MTxClk or posedge Reset)
1265 39 mohor
begin
1266 40 mohor
  if(Reset)
1267 352 olof
    TxStartFrm_sync2 <= 1'b0;
1268 39 mohor
  else
1269 352 olof
    TxStartFrm_sync2 <= TxStartFrm_sync1;
1270 39 mohor
end
1271
 
1272 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1273 38 mohor
begin
1274 40 mohor
  if(Reset)
1275 352 olof
    TxStartFrm_syncb1 <= 1'b0;
1276 38 mohor
  else
1277 352 olof
    TxStartFrm_syncb1 <= TxStartFrm_sync2;
1278 38 mohor
end
1279
 
1280 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1281 38 mohor
begin
1282 40 mohor
  if(Reset)
1283 352 olof
    TxStartFrm_syncb2 <= 1'b0;
1284 38 mohor
  else
1285 352 olof
    TxStartFrm_syncb2 <= TxStartFrm_syncb1;
1286 39 mohor
end
1287
 
1288 40 mohor
always @ (posedge MTxClk or posedge Reset)
1289 39 mohor
begin
1290 40 mohor
  if(Reset)
1291 352 olof
    TxStartFrm <= 1'b0;
1292 38 mohor
  else
1293 39 mohor
  if(TxStartFrm_sync2)
1294 352 olof
    TxStartFrm <= 1'b1;
1295 39 mohor
  else
1296 278 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1297 352 olof
    TxStartFrm <= 1'b0;
1298 38 mohor
end
1299 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1300 38 mohor
 
1301
 
1302 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1303 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1304 38 mohor
begin
1305 40 mohor
  if(Reset)
1306 352 olof
    TxEndFrm_wb <= 1'b0;
1307 38 mohor
  else
1308 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1309 352 olof
    TxEndFrm_wb <= 1'b1;
1310 38 mohor
  else
1311 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1312 352 olof
    TxEndFrm_wb <= 1'b0;
1313 38 mohor
end
1314
 
1315
 
1316
// Marks which bytes are valid within the word.
1317 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1318 38 mohor
 
1319 39 mohor
reg LatchValidBytes;
1320
reg LatchValidBytes_q;
1321 38 mohor
 
1322 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1323 38 mohor
begin
1324 40 mohor
  if(Reset)
1325 352 olof
    LatchValidBytes <= 1'b0;
1326 38 mohor
  else
1327 39 mohor
  if(TxLengthLt4 & TxBDReady)
1328 352 olof
    LatchValidBytes <= 1'b1;
1329 38 mohor
  else
1330 352 olof
    LatchValidBytes <= 1'b0;
1331 38 mohor
end
1332
 
1333 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1334 38 mohor
begin
1335 40 mohor
  if(Reset)
1336 352 olof
    LatchValidBytes_q <= 1'b0;
1337 38 mohor
  else
1338 352 olof
    LatchValidBytes_q <= LatchValidBytes;
1339 38 mohor
end
1340
 
1341
 
1342 39 mohor
// Latching valid bytes
1343 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1344 38 mohor
begin
1345 40 mohor
  if(Reset)
1346 352 olof
    TxValidBytesLatched <= 2'h0;
1347 38 mohor
  else
1348 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1349 352 olof
    TxValidBytesLatched <= TxValidBytes;
1350 39 mohor
  else
1351
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1352 352 olof
    TxValidBytesLatched <= 2'h0;
1353 38 mohor
end
1354
 
1355
 
1356
assign TxIRQEn          = TxStatus[14];
1357 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1358
assign PerPacketPad     = TxStatus[12];
1359
assign PerPacketCrcEn   = TxStatus[11];
1360 38 mohor
 
1361
 
1362 77 mohor
assign RxIRQEn         = RxStatus[14];
1363 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1364 38 mohor
 
1365
 
1366
// Temporary Tx and Rx buffer descriptor address 
1367 329 igorm
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite     & ~WrapTxStatusBit}}   & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
1368
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0])     | // Using first Rx BD
1369
                              {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
1370 38 mohor
 
1371
 
1372
// Latching Tx buffer descriptor address
1373 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1374 38 mohor
begin
1375 40 mohor
  if(Reset)
1376 352 olof
    TxBDAddress <= 7'h0;
1377 321 igorm
  else if (r_TxEn & (~r_TxEn_q))
1378 352 olof
    TxBDAddress <= 7'h0;
1379 321 igorm
  else if (TxStatusWrite)
1380 352 olof
    TxBDAddress <= TempTxBDAddress;
1381 38 mohor
end
1382
 
1383
 
1384
// Latching Rx buffer descriptor address
1385 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1386 38 mohor
begin
1387 40 mohor
  if(Reset)
1388 352 olof
    RxBDAddress <= 7'h0;
1389 321 igorm
  else if(r_RxEn & (~r_RxEn_q))
1390 352 olof
    RxBDAddress <= r_TxBDNum[6:0];
1391 321 igorm
  else if(RxStatusWrite)
1392 352 olof
    RxBDAddress <= TempRxBDAddress;
1393 38 mohor
end
1394
 
1395 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1396 38 mohor
 
1397 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1398 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1399 38 mohor
 
1400 60 mohor
 
1401 38 mohor
// Signals used for various purposes
1402 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1403 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1404
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1405
 
1406
 
1407
 
1408 39 mohor
// Generating delayed signals
1409 40 mohor
always @ (posedge MTxClk or posedge Reset)
1410 38 mohor
begin
1411 40 mohor
  if(Reset)
1412 39 mohor
    begin
1413 352 olof
      TxAbort_q      <= 1'b0;
1414
      TxRetry_q      <= 1'b0;
1415
      TxUsedData_q   <= 1'b0;
1416 39 mohor
    end
1417 38 mohor
  else
1418 39 mohor
    begin
1419 352 olof
      TxAbort_q      <= TxAbort;
1420
      TxRetry_q      <= TxRetry;
1421
      TxUsedData_q   <= TxUsedData;
1422 39 mohor
    end
1423 38 mohor
end
1424
 
1425
// Generating delayed signals
1426 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1427 38 mohor
begin
1428 40 mohor
  if(Reset)
1429 38 mohor
    begin
1430 352 olof
      TxDone_wb_q   <= 1'b0;
1431
      TxAbort_wb_q  <= 1'b0;
1432
      TxRetry_wb_q  <= 1'b0;
1433 38 mohor
    end
1434
  else
1435
    begin
1436 352 olof
      TxDone_wb_q   <= TxDone_wb;
1437
      TxAbort_wb_q  <= TxAbort_wb;
1438
      TxRetry_wb_q  <= TxRetry_wb;
1439 38 mohor
    end
1440
end
1441
 
1442
 
1443 219 mohor
reg TxAbortPacketBlocked;
1444
always @ (posedge WB_CLK_I or posedge Reset)
1445
begin
1446
  if(Reset)
1447 352 olof
    TxAbortPacket <= 1'b0;
1448 219 mohor
  else
1449 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1450
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1451 352 olof
    TxAbortPacket <= 1'b1;
1452 219 mohor
  else
1453 352 olof
    TxAbortPacket <= 1'b0;
1454 219 mohor
end
1455
 
1456
 
1457
always @ (posedge WB_CLK_I or posedge Reset)
1458
begin
1459
  if(Reset)
1460 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1461 221 mohor
  else
1462 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1463 352 olof
    TxAbortPacket_NotCleared <= 1'b0;
1464 272 tadejm
  else
1465 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1466
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1467 352 olof
    TxAbortPacket_NotCleared <= 1'b1;
1468 221 mohor
end
1469
 
1470
 
1471
always @ (posedge WB_CLK_I or posedge Reset)
1472
begin
1473
  if(Reset)
1474 352 olof
    TxAbortPacketBlocked <= 1'b0;
1475 219 mohor
  else
1476 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1477 352 olof
    TxAbortPacketBlocked <= 1'b0;
1478 280 mohor
  else
1479 219 mohor
  if(TxAbortPacket)
1480 352 olof
    TxAbortPacketBlocked <= 1'b1;
1481 219 mohor
end
1482
 
1483
 
1484
reg TxRetryPacketBlocked;
1485
always @ (posedge WB_CLK_I or posedge Reset)
1486
begin
1487
  if(Reset)
1488 352 olof
    TxRetryPacket <= 1'b0;
1489 219 mohor
  else
1490 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1491
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1492 352 olof
    TxRetryPacket <= 1'b1;
1493 219 mohor
  else
1494 352 olof
    TxRetryPacket <= 1'b0;
1495 219 mohor
end
1496
 
1497
 
1498
always @ (posedge WB_CLK_I or posedge Reset)
1499
begin
1500
  if(Reset)
1501 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1502 221 mohor
  else
1503 272 tadejm
  if(StartTxBDRead)
1504 352 olof
    TxRetryPacket_NotCleared <= 1'b0;
1505 272 tadejm
  else
1506 278 mohor
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1507
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1508 352 olof
    TxRetryPacket_NotCleared <= 1'b1;
1509 221 mohor
end
1510
 
1511
 
1512
always @ (posedge WB_CLK_I or posedge Reset)
1513
begin
1514
  if(Reset)
1515 352 olof
    TxRetryPacketBlocked <= 1'b0;
1516 219 mohor
  else
1517 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1518 352 olof
    TxRetryPacketBlocked <= 1'b0;
1519 280 mohor
  else
1520 219 mohor
  if(TxRetryPacket)
1521 352 olof
    TxRetryPacketBlocked <= 1'b1;
1522 219 mohor
end
1523
 
1524
 
1525 221 mohor
reg TxDonePacketBlocked;
1526
always @ (posedge WB_CLK_I or posedge Reset)
1527
begin
1528
  if(Reset)
1529 352 olof
    TxDonePacket <= 1'b0;
1530 221 mohor
  else
1531 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1532
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1533 352 olof
    TxDonePacket <= 1'b1;
1534 221 mohor
  else
1535 352 olof
    TxDonePacket <= 1'b0;
1536 221 mohor
end
1537
 
1538
 
1539
always @ (posedge WB_CLK_I or posedge Reset)
1540
begin
1541
  if(Reset)
1542 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1543 221 mohor
  else
1544 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1545 352 olof
    TxDonePacket_NotCleared <= 1'b0;
1546 272 tadejm
  else
1547 278 mohor
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
1548
     TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1549 352 olof
    TxDonePacket_NotCleared <= 1'b1;
1550 221 mohor
end
1551
 
1552
 
1553
always @ (posedge WB_CLK_I or posedge Reset)
1554
begin
1555
  if(Reset)
1556 352 olof
    TxDonePacketBlocked <= 1'b0;
1557 221 mohor
  else
1558 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1559 352 olof
    TxDonePacketBlocked <= 1'b0;
1560 280 mohor
  else
1561 221 mohor
  if(TxDonePacket)
1562 352 olof
    TxDonePacketBlocked <= 1'b1;
1563 221 mohor
end
1564
 
1565
 
1566 38 mohor
// Indication of the last word
1567 40 mohor
always @ (posedge MTxClk or posedge Reset)
1568 38 mohor
begin
1569 40 mohor
  if(Reset)
1570 352 olof
    LastWord <= 1'b0;
1571 38 mohor
  else
1572
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1573 352 olof
    LastWord <= 1'b0;
1574 38 mohor
  else
1575
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1576 352 olof
    LastWord <= TxEndFrm_wb;
1577 38 mohor
end
1578
 
1579
 
1580
// Tx end frame generation
1581 40 mohor
always @ (posedge MTxClk or posedge Reset)
1582 38 mohor
begin
1583 40 mohor
  if(Reset)
1584 352 olof
    TxEndFrm <= 1'b0;
1585 38 mohor
  else
1586 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1587 352 olof
    TxEndFrm <= 1'b0;
1588 38 mohor
  else
1589
  if(Flop & LastWord)
1590
    begin
1591 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1592 352 olof
        1 : TxEndFrm <= TxByteCnt == 2'h0;
1593
        2 : TxEndFrm <= TxByteCnt == 2'h1;
1594
        3 : TxEndFrm <= TxByteCnt == 2'h2;
1595
 
1596
        default : TxEndFrm <= 1'b0;
1597 38 mohor
      endcase
1598
    end
1599
end
1600
 
1601
 
1602
// Tx data selection (latching)
1603 40 mohor
always @ (posedge MTxClk or posedge Reset)
1604 38 mohor
begin
1605 40 mohor
  if(Reset)
1606 352 olof
    TxData <= 0;
1607 38 mohor
  else
1608 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1609 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1610 352 olof
      2'h0 : TxData <= TxData_wb[31:24];                  // Big Endian Byte Ordering
1611
      2'h1 : TxData <= TxData_wb[23:16];                  // Big Endian Byte Ordering
1612
      2'h2 : TxData <= TxData_wb[15:08];                  // Big Endian Byte Ordering
1613
      2'h3 : TxData <= TxData_wb[07:00];                  // Big Endian Byte Ordering
1614 96 mohor
    endcase
1615 38 mohor
  else
1616 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1617 352 olof
    TxData <= TxData_wb[31:24];                           // Big Endian Byte Ordering
1618 96 mohor
  else
1619 38 mohor
  if(TxUsedData & Flop)
1620
    begin
1621 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1622 352 olof
 
1623
        1 : TxData <= TxDataLatched[23:16];
1624
        2 : TxData <= TxDataLatched[15:8];
1625
        3 : TxData <= TxDataLatched[7:0];
1626 38 mohor
      endcase
1627
    end
1628
end
1629
 
1630
 
1631
// Latching tx data
1632 40 mohor
always @ (posedge MTxClk or posedge Reset)
1633 38 mohor
begin
1634 40 mohor
  if(Reset)
1635 352 olof
    TxDataLatched[31:0] <= 32'h0;
1636 38 mohor
  else
1637 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1638 352 olof
    TxDataLatched[31:0] <= TxData_wb[31:0];
1639 38 mohor
end
1640
 
1641
 
1642
// Tx under run
1643 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1644 38 mohor
begin
1645 40 mohor
  if(Reset)
1646 352 olof
    TxUnderRun_wb <= 1'b0;
1647 38 mohor
  else
1648 39 mohor
  if(TxAbortPulse)
1649 352 olof
    TxUnderRun_wb <= 1'b0;
1650 60 mohor
  else
1651
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1652 352 olof
    TxUnderRun_wb <= 1'b1;
1653 60 mohor
end
1654
 
1655
 
1656 159 mohor
reg TxUnderRun_sync1;
1657
 
1658 60 mohor
// Tx under run
1659
always @ (posedge MTxClk or posedge Reset)
1660
begin
1661
  if(Reset)
1662 352 olof
    TxUnderRun_sync1 <= 1'b0;
1663 43 mohor
  else
1664 60 mohor
  if(TxUnderRun_wb)
1665 352 olof
    TxUnderRun_sync1 <= 1'b1;
1666 60 mohor
  else
1667 159 mohor
  if(BlockingTxStatusWrite_sync2)
1668 352 olof
    TxUnderRun_sync1 <= 1'b0;
1669 159 mohor
end
1670
 
1671
// Tx under run
1672
always @ (posedge MTxClk or posedge Reset)
1673
begin
1674
  if(Reset)
1675 352 olof
    TxUnderRun <= 1'b0;
1676 159 mohor
  else
1677
  if(BlockingTxStatusWrite_sync2)
1678 352 olof
    TxUnderRun <= 1'b0;
1679 159 mohor
  else
1680
  if(TxUnderRun_sync1)
1681 352 olof
    TxUnderRun <= 1'b1;
1682 38 mohor
end
1683
 
1684
 
1685
// Tx Byte counter
1686 40 mohor
always @ (posedge MTxClk or posedge Reset)
1687 38 mohor
begin
1688 40 mohor
  if(Reset)
1689 352 olof
    TxByteCnt <= 2'h0;
1690 38 mohor
  else
1691
  if(TxAbort_q | TxRetry_q)
1692 352 olof
    TxByteCnt <= 2'h0;
1693 38 mohor
  else
1694
  if(TxStartFrm & ~TxUsedData)
1695 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1696 352 olof
      2'h0 : TxByteCnt <= 2'h1;
1697
      2'h1 : TxByteCnt <= 2'h2;
1698
      2'h2 : TxByteCnt <= 2'h3;
1699
      2'h3 : TxByteCnt <= 2'h0;
1700 96 mohor
    endcase
1701 38 mohor
  else
1702
  if(TxUsedData & Flop)
1703 352 olof
    TxByteCnt <= TxByteCnt + 1'b1;
1704 38 mohor
end
1705
 
1706 39 mohor
 
1707 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1708
reg ReadTxDataFromFifo_sync1;
1709
reg ReadTxDataFromFifo_sync2;
1710
reg ReadTxDataFromFifo_sync3;
1711
reg ReadTxDataFromFifo_syncb1;
1712
reg ReadTxDataFromFifo_syncb2;
1713
reg ReadTxDataFromFifo_syncb3;
1714
 
1715
 
1716
always @ (posedge MTxClk or posedge Reset)
1717
begin
1718
  if(Reset)
1719 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1720 150 mohor
  else
1721 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1722 352 olof
     ReadTxDataFromFifo_tck <= 1'b1;
1723 150 mohor
  else
1724
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1725 352 olof
    ReadTxDataFromFifo_tck <= 1'b0;
1726 38 mohor
end
1727
 
1728 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1729 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1730 38 mohor
begin
1731 40 mohor
  if(Reset)
1732 352 olof
    ReadTxDataFromFifo_sync1 <= 1'b0;
1733 38 mohor
  else
1734 352 olof
    ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
1735 39 mohor
end
1736 38 mohor
 
1737 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1738 38 mohor
begin
1739 40 mohor
  if(Reset)
1740 352 olof
    ReadTxDataFromFifo_sync2 <= 1'b0;
1741 38 mohor
  else
1742 352 olof
    ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
1743 38 mohor
end
1744
 
1745 40 mohor
always @ (posedge MTxClk or posedge Reset)
1746 38 mohor
begin
1747 40 mohor
  if(Reset)
1748 352 olof
    ReadTxDataFromFifo_syncb1 <= 1'b0;
1749 38 mohor
  else
1750 352 olof
    ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
1751 38 mohor
end
1752
 
1753 40 mohor
always @ (posedge MTxClk or posedge Reset)
1754 38 mohor
begin
1755 40 mohor
  if(Reset)
1756 352 olof
    ReadTxDataFromFifo_syncb2 <= 1'b0;
1757 38 mohor
  else
1758 352 olof
    ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
1759 38 mohor
end
1760
 
1761 150 mohor
always @ (posedge MTxClk or posedge Reset)
1762
begin
1763
  if(Reset)
1764 352 olof
    ReadTxDataFromFifo_syncb3 <= 1'b0;
1765 150 mohor
  else
1766 352 olof
    ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
1767 150 mohor
end
1768
 
1769 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1770 38 mohor
begin
1771 40 mohor
  if(Reset)
1772 352 olof
    ReadTxDataFromFifo_sync3 <= 1'b0;
1773 38 mohor
  else
1774 352 olof
    ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
1775 38 mohor
end
1776
 
1777 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1778
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1779 38 mohor
 
1780
 
1781 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1782 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1783 38 mohor
begin
1784 40 mohor
  if(Reset)
1785 352 olof
    TxRetrySync1 <= 1'b0;
1786 38 mohor
  else
1787 352 olof
    TxRetrySync1 <= TxRetry;
1788 38 mohor
end
1789
 
1790 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1791 38 mohor
begin
1792 40 mohor
  if(Reset)
1793 352 olof
    TxRetry_wb <= 1'b0;
1794 38 mohor
  else
1795 352 olof
    TxRetry_wb <= TxRetrySync1;
1796 38 mohor
end
1797
 
1798
 
1799 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1800 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1801 38 mohor
begin
1802 40 mohor
  if(Reset)
1803 352 olof
    TxDoneSync1 <= 1'b0;
1804 38 mohor
  else
1805 352 olof
    TxDoneSync1 <= TxDone;
1806 38 mohor
end
1807
 
1808 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1809 38 mohor
begin
1810 40 mohor
  if(Reset)
1811 352 olof
    TxDone_wb <= 1'b0;
1812 38 mohor
  else
1813 352 olof
    TxDone_wb <= TxDoneSync1;
1814 38 mohor
end
1815
 
1816 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1817 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1818 38 mohor
begin
1819 40 mohor
  if(Reset)
1820 352 olof
    TxAbortSync1 <= 1'b0;
1821 38 mohor
  else
1822 352 olof
    TxAbortSync1 <= TxAbort;
1823 38 mohor
end
1824
 
1825 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1826 38 mohor
begin
1827 40 mohor
  if(Reset)
1828 352 olof
    TxAbort_wb <= 1'b0;
1829 38 mohor
  else
1830 352 olof
    TxAbort_wb <= TxAbortSync1;
1831 38 mohor
end
1832
 
1833
 
1834 150 mohor
reg RxAbortSync1;
1835
reg RxAbortSync2;
1836
reg RxAbortSync3;
1837
reg RxAbortSync4;
1838
reg RxAbortSyncb1;
1839
reg RxAbortSyncb2;
1840 39 mohor
 
1841 333 igorm
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
1842 150 mohor
 
1843 40 mohor
// Reading the Rx buffer descriptor
1844
always @ (posedge WB_CLK_I or posedge Reset)
1845
begin
1846
  if(Reset)
1847 352 olof
    RxBDRead <= 1'b0;
1848 40 mohor
  else
1849 166 mohor
  if(StartRxBDRead & ~RxReady)
1850 352 olof
    RxBDRead <= 1'b1;
1851 40 mohor
  else
1852
  if(RxBDReady)
1853 352 olof
    RxBDRead <= 1'b0;
1854 40 mohor
end
1855 39 mohor
 
1856
 
1857 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1858
// written to the previous one.
1859
 
1860
// Latching READY status of the Rx buffer descriptor
1861 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1862 38 mohor
begin
1863 40 mohor
  if(Reset)
1864 352 olof
    RxBDReady <= 1'b0;
1865 38 mohor
  else
1866 166 mohor
  if(RxPointerRead)
1867 352 olof
    RxBDReady <= 1'b0;
1868 150 mohor
  else
1869 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1870 352 olof
    RxBDReady <= ram_do[15]; // RxBDReady is sampled only once at the beginning
1871 38 mohor
end
1872
 
1873 40 mohor
// Latching Rx buffer descriptor status
1874
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1875
always @ (posedge WB_CLK_I or posedge Reset)
1876 38 mohor
begin
1877 40 mohor
  if(Reset)
1878 352 olof
    RxStatus <= 2'h0;
1879 38 mohor
  else
1880 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1881 352 olof
    RxStatus <= ram_do[14:13];
1882 38 mohor
end
1883
 
1884
 
1885 166 mohor
// RxReady generation
1886
always @ (posedge WB_CLK_I or posedge Reset)
1887
begin
1888
  if(Reset)
1889 352 olof
    RxReady <= 1'b0;
1890 166 mohor
  else
1891 333 igorm
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
1892 352 olof
    RxReady <= 1'b0;
1893 166 mohor
  else
1894
  if(RxEn & RxEn_q & RxPointerRead)
1895 352 olof
    RxReady <= 1'b1;
1896 166 mohor
end
1897 38 mohor
 
1898
 
1899 40 mohor
// Reading Rx BD pointer
1900
 
1901
 
1902
assign StartRxPointerRead = RxBDRead & RxBDReady;
1903
 
1904
// Reading Tx BD Pointer
1905
always @ (posedge WB_CLK_I or posedge Reset)
1906 38 mohor
begin
1907 40 mohor
  if(Reset)
1908 352 olof
    RxPointerRead <= 1'b0;
1909 38 mohor
  else
1910 40 mohor
  if(StartRxPointerRead)
1911 352 olof
    RxPointerRead <= 1'b1;
1912 38 mohor
  else
1913 166 mohor
  if(RxEn & RxEn_q)
1914 352 olof
    RxPointerRead <= 1'b0;
1915 38 mohor
end
1916
 
1917 113 mohor
 
1918 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1919
always @ (posedge WB_CLK_I or posedge Reset)
1920
begin
1921
  if(Reset)
1922 352 olof
    RxPointerMSB <= 30'h0;
1923 40 mohor
  else
1924
  if(RxEn & RxEn_q & RxPointerRead)
1925 352 olof
    RxPointerMSB <= ram_do[31:2];
1926 40 mohor
  else
1927 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1928 352 olof
      RxPointerMSB <= RxPointerMSB + 1'b1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1929 40 mohor
end
1930 38 mohor
 
1931
 
1932 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1933 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1934
begin
1935
  if(Reset)
1936 352 olof
    RxPointerLSB_rst[1:0] <= 0;
1937 96 mohor
  else
1938 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1939 352 olof
    RxPointerLSB_rst[1:0] <= 0;
1940 96 mohor
  else
1941
  if(RxEn & RxEn_q & RxPointerRead)
1942 352 olof
    RxPointerLSB_rst[1:0] <= ram_do[1:0];
1943 96 mohor
end
1944
 
1945
 
1946 159 mohor
always @ (RxPointerLSB_rst)
1947 96 mohor
begin
1948 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1949
    2'h0 : RxByteSel[3:0] = 4'hf;
1950
    2'h1 : RxByteSel[3:0] = 4'h7;
1951
    2'h2 : RxByteSel[3:0] = 4'h3;
1952
    2'h3 : RxByteSel[3:0] = 4'h1;
1953 96 mohor
  endcase
1954
end
1955
 
1956
 
1957
always @ (posedge WB_CLK_I or posedge Reset)
1958
begin
1959
  if(Reset)
1960 352 olof
    RxEn_needed <= 1'b0;
1961 38 mohor
  else
1962 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1963 352 olof
    RxEn_needed <= 1'b1;
1964 38 mohor
  else
1965 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1966 352 olof
    RxEn_needed <= 1'b0;
1967 38 mohor
end
1968
 
1969
 
1970 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1971
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1972 38 mohor
 
1973 40 mohor
reg RxEnableWindow;
1974 38 mohor
 
1975
// Indicating that last byte is being reveived
1976 40 mohor
always @ (posedge MRxClk or posedge Reset)
1977 38 mohor
begin
1978 40 mohor
  if(Reset)
1979 352 olof
    LastByteIn <= 1'b0;
1980 38 mohor
  else
1981 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1982 352 olof
    LastByteIn <= 1'b0;
1983 38 mohor
  else
1984 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1985 352 olof
    LastByteIn <= 1'b1;
1986 38 mohor
end
1987
 
1988 159 mohor
reg ShiftEnded_rck;
1989 40 mohor
reg ShiftEndedSync1;
1990
reg ShiftEndedSync2;
1991 118 mohor
reg ShiftEndedSync3;
1992
reg ShiftEndedSync_c1;
1993
reg ShiftEndedSync_c2;
1994
 
1995 40 mohor
wire StartShiftWillEnd;
1996 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1997 38 mohor
 
1998
// Indicating that data reception will end
1999 40 mohor
always @ (posedge MRxClk or posedge Reset)
2000 38 mohor
begin
2001 40 mohor
  if(Reset)
2002 352 olof
    ShiftWillEnd <= 1'b0;
2003 38 mohor
  else
2004 159 mohor
  if(ShiftEnded_rck | RxAbort)
2005 352 olof
    ShiftWillEnd <= 1'b0;
2006 38 mohor
  else
2007 40 mohor
  if(StartShiftWillEnd)
2008 352 olof
    ShiftWillEnd <= 1'b1;
2009 38 mohor
end
2010
 
2011
 
2012 40 mohor
 
2013 38 mohor
// Receive byte counter
2014 40 mohor
always @ (posedge MRxClk or posedge Reset)
2015 38 mohor
begin
2016 40 mohor
  if(Reset)
2017 352 olof
    RxByteCnt <= 2'h0;
2018 38 mohor
  else
2019 159 mohor
  if(ShiftEnded_rck | RxAbort)
2020 352 olof
    RxByteCnt <= 2'h0;
2021 97 lampret
  else
2022 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2023 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2024 352 olof
      2'h0 : RxByteCnt <= 2'h1;
2025
      2'h1 : RxByteCnt <= 2'h2;
2026
      2'h2 : RxByteCnt <= 2'h3;
2027
      2'h3 : RxByteCnt <= 2'h0;
2028 96 mohor
    endcase
2029 38 mohor
  else
2030 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2031 352 olof
    RxByteCnt <= RxByteCnt + 1'b1;
2032 38 mohor
end
2033
 
2034
 
2035
// Indicates how many bytes are valid within the last word
2036 40 mohor
always @ (posedge MRxClk or posedge Reset)
2037 38 mohor
begin
2038 40 mohor
  if(Reset)
2039 352 olof
    RxValidBytes <= 2'h1;
2040 38 mohor
  else
2041 96 mohor
  if(RxValid & RxStartFrm)
2042 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2043 352 olof
      2'h0 : RxValidBytes <= 2'h1;
2044
      2'h1 : RxValidBytes <= 2'h2;
2045
      2'h2 : RxValidBytes <= 2'h3;
2046
      2'h3 : RxValidBytes <= 2'h0;
2047 96 mohor
    endcase
2048 38 mohor
  else
2049 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2050 352 olof
    RxValidBytes <= RxValidBytes + 1'b1;
2051 38 mohor
end
2052
 
2053
 
2054 40 mohor
always @ (posedge MRxClk or posedge Reset)
2055 38 mohor
begin
2056 40 mohor
  if(Reset)
2057 352 olof
    RxDataLatched1       <= 24'h0;
2058 38 mohor
  else
2059 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2060 96 mohor
    if(RxStartFrm)
2061 40 mohor
    begin
2062 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2063 352 olof
        2'h0:        RxDataLatched1[31:24] <= RxData;            // Big Endian Byte Ordering
2064
        2'h1:        RxDataLatched1[23:16] <= RxData;
2065
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2066
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2067 96 mohor
      endcase
2068
    end
2069
    else if (RxEnableWindow)
2070
    begin
2071 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2072 352 olof
        2'h0:        RxDataLatched1[31:24] <= RxData;            // Big Endian Byte Ordering
2073
        2'h1:        RxDataLatched1[23:16] <= RxData;
2074
        2'h2:        RxDataLatched1[15:8]  <= RxData;
2075
        2'h3:        RxDataLatched1        <= RxDataLatched1;
2076 40 mohor
      endcase
2077
    end
2078 38 mohor
end
2079
 
2080 40 mohor
wire SetWriteRxDataToFifo;
2081 38 mohor
 
2082 40 mohor
// Assembling data that will be written to the rx_fifo
2083
always @ (posedge MRxClk or posedge Reset)
2084 38 mohor
begin
2085 40 mohor
  if(Reset)
2086 352 olof
    RxDataLatched2 <= 32'h0;
2087 38 mohor
  else
2088 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2089 352 olof
    RxDataLatched2 <= {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2090 38 mohor
  else
2091 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2092 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2093 352 olof
 
2094
      1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
2095
      2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
2096
      3 : RxDataLatched2 <= {RxDataLatched1[31:8],   8'h0};
2097 40 mohor
    endcase
2098 38 mohor
end
2099
 
2100
 
2101 40 mohor
reg WriteRxDataToFifoSync1;
2102
reg WriteRxDataToFifoSync2;
2103 150 mohor
reg WriteRxDataToFifoSync3;
2104 38 mohor
 
2105
 
2106 40 mohor
// Indicating start of the reception process
2107 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2108
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2109
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2110 38 mohor
 
2111 150 mohor
always @ (posedge MRxClk or posedge Reset)
2112
begin
2113
  if(Reset)
2114 352 olof
    WriteRxDataToFifo <= 1'b0;
2115 150 mohor
  else
2116
  if(SetWriteRxDataToFifo & ~RxAbort)
2117 352 olof
    WriteRxDataToFifo <= 1'b1;
2118 150 mohor
  else
2119
  if(WriteRxDataToFifoSync2 | RxAbort)
2120 352 olof
    WriteRxDataToFifo <= 1'b0;
2121 150 mohor
end
2122 40 mohor
 
2123 150 mohor
 
2124
 
2125
always @ (posedge WB_CLK_I or posedge Reset)
2126
begin
2127
  if(Reset)
2128 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2129 150 mohor
  else
2130
  if(WriteRxDataToFifo)
2131 352 olof
    WriteRxDataToFifoSync1 <= 1'b1;
2132 150 mohor
  else
2133 352 olof
    WriteRxDataToFifoSync1 <= 1'b0;
2134 150 mohor
end
2135
 
2136
always @ (posedge WB_CLK_I or posedge Reset)
2137
begin
2138
  if(Reset)
2139 352 olof
    WriteRxDataToFifoSync2 <= 1'b0;
2140 150 mohor
  else
2141 352 olof
    WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
2142 150 mohor
end
2143
 
2144
always @ (posedge WB_CLK_I or posedge Reset)
2145
begin
2146
  if(Reset)
2147 352 olof
    WriteRxDataToFifoSync3 <= 1'b0;
2148 150 mohor
  else
2149 352 olof
    WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
2150 150 mohor
end
2151
 
2152
wire WriteRxDataToFifo_wb;
2153
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2154
 
2155
 
2156 90 mohor
reg LatchedRxStartFrm;
2157
reg SyncRxStartFrm;
2158
reg SyncRxStartFrm_q;
2159 150 mohor
reg SyncRxStartFrm_q2;
2160 90 mohor
wire RxFifoReset;
2161 40 mohor
 
2162 90 mohor
always @ (posedge MRxClk or posedge Reset)
2163
begin
2164
  if(Reset)
2165 352 olof
    LatchedRxStartFrm <= 0;
2166 90 mohor
  else
2167 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2168 352 olof
    LatchedRxStartFrm <= 1;
2169 90 mohor
  else
2170 150 mohor
  if(SyncRxStartFrm_q)
2171 352 olof
    LatchedRxStartFrm <= 0;
2172 90 mohor
end
2173
 
2174
 
2175
always @ (posedge WB_CLK_I or posedge Reset)
2176
begin
2177
  if(Reset)
2178 352 olof
    SyncRxStartFrm <= 0;
2179 90 mohor
  else
2180
  if(LatchedRxStartFrm)
2181 352 olof
    SyncRxStartFrm <= 1;
2182 90 mohor
  else
2183 352 olof
    SyncRxStartFrm <= 0;
2184 90 mohor
end
2185
 
2186
 
2187
always @ (posedge WB_CLK_I or posedge Reset)
2188
begin
2189
  if(Reset)
2190 352 olof
    SyncRxStartFrm_q <= 0;
2191 90 mohor
  else
2192 352 olof
    SyncRxStartFrm_q <= SyncRxStartFrm;
2193 90 mohor
end
2194
 
2195 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2196
begin
2197
  if(Reset)
2198 352 olof
    SyncRxStartFrm_q2 <= 0;
2199 150 mohor
  else
2200 352 olof
    SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
2201 150 mohor
end
2202 90 mohor
 
2203
 
2204 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2205 90 mohor
 
2206 349 olof
eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH),
2207
           .DEPTH(RX_FIFO_DEPTH),
2208 352 olof
           .CNT_WIDTH(RX_FIFO_CNT_WIDTH))
2209 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2210
         .clk(WB_CLK_I),                                .reset(Reset),
2211 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2212 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2213 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2214 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2215 88 mohor
        );
2216 40 mohor
 
2217 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2218
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2219 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2220 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2221 40 mohor
 
2222
 
2223
// Generation of the end-of-frame signal
2224
always @ (posedge MRxClk or posedge Reset)
2225 38 mohor
begin
2226 40 mohor
  if(Reset)
2227 352 olof
    ShiftEnded_rck <= 1'b0;
2228 38 mohor
  else
2229 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2230 352 olof
    ShiftEnded_rck <= 1'b1;
2231 38 mohor
  else
2232 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2233 352 olof
    ShiftEnded_rck <= 1'b0;
2234 38 mohor
end
2235
 
2236 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2237
begin
2238
  if(Reset)
2239 352 olof
    ShiftEndedSync1 <= 1'b0;
2240 40 mohor
  else
2241 352 olof
    ShiftEndedSync1 <= ShiftEnded_rck;
2242 40 mohor
end
2243 38 mohor
 
2244 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2245 38 mohor
begin
2246 40 mohor
  if(Reset)
2247 352 olof
    ShiftEndedSync2 <= 1'b0;
2248 38 mohor
  else
2249 352 olof
    ShiftEndedSync2 <= ShiftEndedSync1;
2250 40 mohor
end
2251 38 mohor
 
2252 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2253
begin
2254
  if(Reset)
2255 352 olof
    ShiftEndedSync3 <= 1'b0;
2256 118 mohor
  else
2257
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2258 352 olof
    ShiftEndedSync3 <= 1'b1;
2259 118 mohor
  else
2260
  if(ShiftEnded)
2261 352 olof
    ShiftEndedSync3 <= 1'b0;
2262 118 mohor
end
2263 38 mohor
 
2264 40 mohor
// Generation of the end-of-frame signal
2265
always @ (posedge WB_CLK_I or posedge Reset)
2266 38 mohor
begin
2267 40 mohor
  if(Reset)
2268 352 olof
    ShiftEnded <= 1'b0;
2269 38 mohor
  else
2270 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2271 352 olof
    ShiftEnded <= 1'b1;
2272 38 mohor
  else
2273 40 mohor
  if(RxStatusWrite)
2274 352 olof
    ShiftEnded <= 1'b0;
2275 38 mohor
end
2276
 
2277 118 mohor
always @ (posedge MRxClk or posedge Reset)
2278
begin
2279
  if(Reset)
2280 352 olof
    ShiftEndedSync_c1 <= 1'b0;
2281 118 mohor
  else
2282 352 olof
    ShiftEndedSync_c1 <= ShiftEndedSync2;
2283 118 mohor
end
2284 38 mohor
 
2285 118 mohor
always @ (posedge MRxClk or posedge Reset)
2286
begin
2287
  if(Reset)
2288 352 olof
    ShiftEndedSync_c2 <= 1'b0;
2289 118 mohor
  else
2290 352 olof
    ShiftEndedSync_c2 <= ShiftEndedSync_c1;
2291 118 mohor
end
2292
 
2293 40 mohor
// Generation of the end-of-frame signal
2294
always @ (posedge MRxClk or posedge Reset)
2295 38 mohor
begin
2296 40 mohor
  if(Reset)
2297 352 olof
    RxEnableWindow <= 1'b0;
2298 38 mohor
  else
2299 40 mohor
  if(RxStartFrm)
2300 352 olof
    RxEnableWindow <= 1'b1;
2301 38 mohor
  else
2302 40 mohor
  if(RxEndFrm | RxAbort)
2303 352 olof
    RxEnableWindow <= 1'b0;
2304 38 mohor
end
2305
 
2306
 
2307 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2308 38 mohor
begin
2309 40 mohor
  if(Reset)
2310 352 olof
    RxAbortSync1 <= 1'b0;
2311 38 mohor
  else
2312 352 olof
    RxAbortSync1 <= RxAbortLatched;
2313 40 mohor
end
2314
 
2315
always @ (posedge WB_CLK_I or posedge Reset)
2316
begin
2317
  if(Reset)
2318 352 olof
    RxAbortSync2 <= 1'b0;
2319 38 mohor
  else
2320 352 olof
    RxAbortSync2 <= RxAbortSync1;
2321 38 mohor
end
2322
 
2323 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2324
begin
2325
  if(Reset)
2326 352 olof
    RxAbortSync3 <= 1'b0;
2327 150 mohor
  else
2328 352 olof
    RxAbortSync3 <= RxAbortSync2;
2329 150 mohor
end
2330
 
2331
always @ (posedge WB_CLK_I or posedge Reset)
2332
begin
2333
  if(Reset)
2334 352 olof
    RxAbortSync4 <= 1'b0;
2335 150 mohor
  else
2336 352 olof
    RxAbortSync4 <= RxAbortSync3;
2337 150 mohor
end
2338
 
2339 40 mohor
always @ (posedge MRxClk or posedge Reset)
2340
begin
2341
  if(Reset)
2342 352 olof
    RxAbortSyncb1 <= 1'b0;
2343 40 mohor
  else
2344 352 olof
    RxAbortSyncb1 <= RxAbortSync2;
2345 40 mohor
end
2346 38 mohor
 
2347 40 mohor
always @ (posedge MRxClk or posedge Reset)
2348 38 mohor
begin
2349 40 mohor
  if(Reset)
2350 352 olof
    RxAbortSyncb2 <= 1'b0;
2351 38 mohor
  else
2352 352 olof
    RxAbortSyncb2 <= RxAbortSyncb1;
2353 38 mohor
end
2354
 
2355
 
2356 64 mohor
always @ (posedge MRxClk or posedge Reset)
2357
begin
2358
  if(Reset)
2359 352 olof
    RxAbortLatched <= 1'b0;
2360 64 mohor
  else
2361 150 mohor
  if(RxAbortSyncb2)
2362 352 olof
    RxAbortLatched <= 1'b0;
2363 150 mohor
  else
2364 64 mohor
  if(RxAbort)
2365 352 olof
    RxAbortLatched <= 1'b1;
2366 64 mohor
end
2367 40 mohor
 
2368 64 mohor
 
2369 42 mohor
always @ (posedge MRxClk or posedge Reset)
2370
begin
2371
  if(Reset)
2372 352 olof
    LatchedRxLength[15:0] <= 16'h0;
2373 42 mohor
  else
2374 150 mohor
  if(LoadRxStatus)
2375 352 olof
    LatchedRxLength[15:0] <= RxLength[15:0];
2376 42 mohor
end
2377
 
2378
 
2379 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2380 42 mohor
 
2381
always @ (posedge MRxClk or posedge Reset)
2382
begin
2383
  if(Reset)
2384 352 olof
    RxStatusInLatched <= 'h0;
2385 42 mohor
  else
2386 150 mohor
  if(LoadRxStatus)
2387 352 olof
    RxStatusInLatched <= RxStatusIn;
2388 42 mohor
end
2389
 
2390
 
2391 60 mohor
// Rx overrun
2392
always @ (posedge WB_CLK_I or posedge Reset)
2393
begin
2394
  if(Reset)
2395 352 olof
    RxOverrun <= 1'b0;
2396 60 mohor
  else
2397
  if(RxStatusWrite)
2398 352 olof
    RxOverrun <= 1'b0;
2399 60 mohor
  else
2400
  if(RxBufferFull & WriteRxDataToFifo_wb)
2401 352 olof
    RxOverrun <= 1'b1;
2402 60 mohor
end
2403 48 mohor
 
2404 77 mohor
 
2405
 
2406
wire TxError;
2407
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2408
 
2409
wire RxError;
2410
 
2411 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2412 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2413
// AddressMiss is identifying that a frame was received because of the promiscous
2414
// mode and is not an error
2415 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2416
 
2417 272 tadejm
 
2418
 
2419
reg RxStatusWriteLatched;
2420
reg RxStatusWriteLatched_sync1;
2421
reg RxStatusWriteLatched_sync2;
2422
reg RxStatusWriteLatched_syncb1;
2423
reg RxStatusWriteLatched_syncb2;
2424
 
2425
 
2426
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
2427
always @ (posedge WB_CLK_I or posedge Reset)
2428
begin
2429
  if(Reset)
2430 352 olof
    RxStatusWriteLatched <= 1'b0;
2431 272 tadejm
  else
2432
  if(RxStatusWriteLatched_syncb2)
2433 352 olof
    RxStatusWriteLatched <= 1'b0;
2434 272 tadejm
  else
2435
  if(RxStatusWrite)
2436 352 olof
    RxStatusWriteLatched <= 1'b1;
2437 272 tadejm
end
2438
 
2439
 
2440
always @ (posedge MRxClk or posedge Reset)
2441
begin
2442
  if(Reset)
2443
    begin
2444 352 olof
      RxStatusWriteLatched_sync1 <= 1'b0;
2445
      RxStatusWriteLatched_sync2 <= 1'b0;
2446 272 tadejm
    end
2447
  else
2448
    begin
2449 352 olof
      RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
2450
      RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
2451 272 tadejm
    end
2452
end
2453
 
2454
 
2455
always @ (posedge WB_CLK_I or posedge Reset)
2456
begin
2457
  if(Reset)
2458
    begin
2459 352 olof
      RxStatusWriteLatched_syncb1 <= 1'b0;
2460
      RxStatusWriteLatched_syncb2 <= 1'b0;
2461 272 tadejm
    end
2462
  else
2463
    begin
2464 352 olof
      RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
2465
      RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
2466 272 tadejm
    end
2467
end
2468
 
2469
 
2470
 
2471 77 mohor
// Tx Done Interrupt
2472
always @ (posedge WB_CLK_I or posedge Reset)
2473
begin
2474
  if(Reset)
2475 352 olof
    TxB_IRQ <= 1'b0;
2476 77 mohor
  else
2477
  if(TxStatusWrite & TxIRQEn)
2478 352 olof
    TxB_IRQ <= ~TxError;
2479 77 mohor
  else
2480 352 olof
    TxB_IRQ <= 1'b0;
2481 77 mohor
end
2482
 
2483
 
2484
// Tx Error Interrupt
2485
always @ (posedge WB_CLK_I or posedge Reset)
2486
begin
2487
  if(Reset)
2488 352 olof
    TxE_IRQ <= 1'b0;
2489 77 mohor
  else
2490
  if(TxStatusWrite & TxIRQEn)
2491 352 olof
    TxE_IRQ <= TxError;
2492 77 mohor
  else
2493 352 olof
    TxE_IRQ <= 1'b0;
2494 77 mohor
end
2495