OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Blame information for rev 364

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3 364 olof
////  ethmac.v                                                    ////
4 15 mohor
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41 364 olof
// 2011-08-09 olof@opencores.org
42
// Renamed from eth_top.v to ethmac.v to better fit into the OpenCores
43
// Structure
44
//
45 15 mohor
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48 333 igorm
// Revision 1.51  2005/02/21 11:13:17  igorm
49
// Defer indication fixed.
50
//
51 327 igorm
// Revision 1.50  2004/04/26 15:26:23  igorm
52
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
53
//   previous update of the core.
54
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
55
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
56
//   register. (thanks to Mathias and Torbjorn)
57
// - Multicast reception was fixed. Thanks to Ulrich Gries
58
//
59 321 igorm
// Revision 1.49  2003/11/12 18:24:59  tadejm
60
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
61
//
62 304 tadejm
// Revision 1.48  2003/10/17 07:46:16  markom
63
// mbist signals updated according to newest convention
64
//
65 302 markom
// Revision 1.47  2003/10/06 15:43:45  knguyen
66
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
67
//
68 301 knguyen
// Revision 1.46  2003/01/30 13:30:22  tadejm
69
// Defer indication changed.
70
//
71 276 tadejm
// Revision 1.45  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.44  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.43  2002/11/22 01:57:06  mohor
79
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
80
// synchronized.
81
//
82 261 mohor
// Revision 1.42  2002/11/21 00:09:19  mohor
83
// TPauseRq synchronized to tx_clk.
84
//
85 255 mohor
// Revision 1.41  2002/11/19 18:13:49  mohor
86
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
87
//
88 253 mohor
// Revision 1.40  2002/11/19 17:34:25  mohor
89
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
90
// that a frame was received because of the promiscous mode.
91
//
92 250 mohor
// Revision 1.39  2002/11/18 17:31:55  mohor
93
// wb_rst_i is used for MIIM reset.
94
//
95 248 mohor
// Revision 1.38  2002/11/14 18:37:20  mohor
96
// r_Rst signal does not reset any module any more and is removed from the design.
97
//
98 244 mohor
// Revision 1.37  2002/11/13 22:25:36  tadejm
99
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
100
//
101 240 tadejm
// Revision 1.36  2002/10/18 17:04:20  tadejm
102
// Changed BIST scan signals.
103
//
104 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
105
// Typo error fixed. (When using Bist)
106
//
107 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
108
// Signals for WISHBONE B3 compliant interface added.
109
//
110 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
111
// BIST added.
112
//
113 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
114
// CsMiss added. When address between 0x800 and 0xfff is accessed within
115
// Ethernet Core, error acknowledge is generated.
116
//
117 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
118
// CarrierSenseLost bug fixed when operating in full duplex mode.
119
//
120 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
121
// Ethernet debug registers removed.
122
//
123 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
124
// Error acknowledge is generated when accessing BDs and RST bit in the
125
// MODER register (r_Rst) is set.
126
//
127 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
128
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
129
// connected.
130
//
131 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
132
// RxAbort changed. Packets received with MRxErr (from PHY) are also
133
// aborted.
134
//
135 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
136
// EXTERNAL_DMA removed. External DMA not supported.
137
//
138 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
139
// Outputs registered. Reset changed for eth_wishbone module.
140
//
141 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
142
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
143
// selected in eth_defines.v
144
//
145 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
146
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
147
// name was incorrect.
148
//
149 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
150
// Small fixes for external/internal DMA missmatches.
151
//
152 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
153
// Interrupts changed in the top file
154
//
155 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
156
// Small fixes.
157
//
158 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
159
// Registered trimmed. Unused registers removed.
160
//
161 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
162
// EXTERNAL_DMA used instead of WISHBONE_DMA.
163
//
164 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
165
// Testbench fixed, code simplified, unused signals removed.
166
//
167 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
168
// RxAbort is connected differently.
169
//
170 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
171
// Changes that were lost when updating from 1.11 to 1.14 fixed.
172
//
173 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
174
// Modified for Address Checking,
175
// addition of eth_addrcheck.v
176
//
177
// Revision 1.13  2002/02/12 17:03:03  mohor
178
// HASH0 and HASH1 registers added. Registers address width was
179
// changed to 8 bits.
180
//
181
// Revision 1.12  2002/02/11 09:18:22  mohor
182
// Tx status is written back to the BD.
183
//
184 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
185
// Rx status is written back to the BD.
186
//
187 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
188
// non-DMA host interface added. Select the right configutation in eth_defines.
189
//
190 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
191
// Link in the header changed.
192
//
193 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
194
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
195
// instead of the number of RX descriptors).
196
//
197 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
198
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
199
//
200 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
201
// Number of addresses (wb_adr_i) minimized.
202
//
203 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
204
// eth_timescale.v changed to timescale.v This is done because of the
205
// simulation of the few cores in a one joined project.
206
//
207 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
208
// Status signals changed, Adress decoding changed, interrupt controller
209
// added.
210
//
211 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
212
// Defines changed (All precede with ETH_). Small changes because some
213
// tools generate warnings when two operands are together. Synchronization
214
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
215
// demands).
216
//
217 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
218
// Signal names changed on the top level for easier pad insertion (ASIC).
219
//
220 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
221
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
222
// Include files fixed to contain no path.
223
// File names and module names changed ta have a eth_ prologue in the name.
224
// File eth_timescale.v is used to define timescale
225
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
226
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
227
// and Mdo_OE. The bidirectional signal must be created on the top level. This
228
// is done due to the ASIC tools.
229
//
230 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
231
// Unconnected signals are now connected.
232
//
233
// Revision 1.1  2001/07/30 21:23:42  mohor
234
// Directory structure changed. Files checked and joind together.
235
//
236
//
237
//
238 20 mohor
// 
239 15 mohor
 
240
 
241 356 olof
`include "ethmac_defines.v"
242 22 mohor
`include "timescale.v"
243 15 mohor
 
244
 
245 364 olof
module ethmac
246 15 mohor
(
247
  // WISHBONE common
248 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
249 15 mohor
 
250
  // WISHBONE slave
251 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
252 15 mohor
 
253 41 mohor
  // WISHBONE master
254
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
255
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
256
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
257
 
258 214 mohor
`ifdef ETH_WISHBONE_B3
259
  m_wb_cti_o, m_wb_bte_o,
260
`endif
261
 
262 15 mohor
  //TX
263 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
264 15 mohor
 
265
  //RX
266 20 mohor
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
267 15 mohor
 
268
  // MIIM
269 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
270 17 mohor
 
271 21 mohor
  int_o
272 17 mohor
 
273 210 mohor
  // Bist
274
`ifdef ETH_BIST
275 227 tadejm
  ,
276
  // debug chain signals
277 302 markom
  mbist_si_i,       // bist scan serial in
278
  mbist_so_o,       // bist scan serial out
279
  mbist_ctrl_i        // bist chain shift control
280 210 mohor
`endif
281 21 mohor
 
282 15 mohor
);
283
 
284
 
285 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
286
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
287
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
288
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
289
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
290
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
291 15 mohor
 
292
 
293
// WISHBONE common
294 17 mohor
input           wb_clk_i;     // WISHBONE clock
295
input           wb_rst_i;     // WISHBONE reset
296
input   [31:0]  wb_dat_i;     // WISHBONE data input
297
output  [31:0]  wb_dat_o;     // WISHBONE data output
298
output          wb_err_o;     // WISHBONE error output
299 15 mohor
 
300
// WISHBONE slave
301 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
302 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
303
input           wb_we_i;      // WISHBONE write enable input
304
input           wb_cyc_i;     // WISHBONE cycle input
305
input           wb_stb_i;     // WISHBONE strobe input
306
output          wb_ack_o;     // WISHBONE acknowledge output
307 15 mohor
 
308 41 mohor
// WISHBONE master
309
output  [31:0]  m_wb_adr_o;
310
output   [3:0]  m_wb_sel_o;
311
output          m_wb_we_o;
312
input   [31:0]  m_wb_dat_i;
313
output  [31:0]  m_wb_dat_o;
314
output          m_wb_cyc_o;
315
output          m_wb_stb_o;
316
input           m_wb_ack_i;
317
input           m_wb_err_i;
318 15 mohor
 
319 327 igorm
wire    [29:0]  m_wb_adr_tmp;
320
 
321 214 mohor
`ifdef ETH_WISHBONE_B3
322
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
323
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
324
`endif
325 41 mohor
 
326 15 mohor
// Tx
327 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
328 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
329
output          mtxen_pad_o;   // Transmit enable (to PHY)
330
output          mtxerr_pad_o;  // Transmit error (to PHY)
331 15 mohor
 
332
// Rx
333 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
334 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
335
input           mrxdv_pad_i;   // Receive data valid (from PHY)
336
input           mrxerr_pad_i;  // Receive data error (from PHY)
337 15 mohor
 
338
// Common Tx and Rx
339 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
340
input           mcrs_pad_i;    // Carrier sense (from PHY)
341 15 mohor
 
342
// MII Management interface
343 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
344
output          mdc_pad_o;     // MII Management data clock (to PHY)
345
output          md_pad_o;      // MII data output (to I/O cell)
346 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
347 15 mohor
 
348 21 mohor
output          int_o;         // Interrupt output
349 15 mohor
 
350 210 mohor
// Bist
351
`ifdef ETH_BIST
352 302 markom
input   mbist_si_i;       // bist scan serial in
353
output  mbist_so_o;       // bist scan serial out
354
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
355 210 mohor
`endif
356
 
357 360 olof
wire    [31:0]  wb_dbg_dat0;
358
 
359 15 mohor
wire     [7:0]  r_ClkDiv;
360
wire            r_MiiNoPre;
361
wire    [15:0]  r_CtrlData;
362
wire     [4:0]  r_FIAD;
363
wire     [4:0]  r_RGAD;
364
wire            r_WCtrlData;
365
wire            r_RStat;
366
wire            r_ScanStat;
367
wire            NValid_stat;
368
wire            Busy_stat;
369
wire            LinkFail;
370
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
371
wire            WCtrlDataStart;
372
wire            RStatStart;
373
wire            UpdateMIIRX_DATAReg;
374
 
375
wire            TxStartFrm;
376
wire            TxEndFrm;
377
wire            TxUsedData;
378
wire     [7:0]  TxData;
379
wire            TxRetry;
380
wire            TxAbort;
381
wire            TxUnderRun;
382
wire            TxDone;
383
 
384
 
385 149 mohor
reg             WillSendControlFrame_sync1;
386
reg             WillSendControlFrame_sync2;
387
reg             WillSendControlFrame_sync3;
388
reg             RstTxPauseRq;
389 15 mohor
 
390 255 mohor
reg             TxPauseRq_sync1;
391
reg             TxPauseRq_sync2;
392
reg             TxPauseRq_sync3;
393
reg             TPauseRq;
394 15 mohor
 
395 255 mohor
 
396 15 mohor
// Connecting Miim module
397 352 olof
eth_miim miim1
398 15 mohor
(
399 248 mohor
  .Clk(wb_clk_i),                         .Reset(wb_rst_i),                   .Divider(r_ClkDiv),
400 15 mohor
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
401
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
402 17 mohor
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
403 95 mohor
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
404 15 mohor
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
405
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
406
);
407
 
408
 
409
 
410
 
411 304 tadejm
wire  [3:0] RegCs;          // Connected to registers
412 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
413 42 mohor
wire        r_RecSmall;     // Receive small frames
414 15 mohor
wire        r_LoopBck;      // Loopback
415
wire        r_TxEn;         // Tx Enable
416
wire        r_RxEn;         // Rx Enable
417
 
418
wire        MRxDV_Lb;       // Muxed MII receive data valid
419
wire        MRxErr_Lb;      // Muxed MII Receive Error
420
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
421
wire        Transmitting;   // Indication that TxEthMAC is transmitting
422
wire        r_HugEn;        // Huge packet enable
423
wire        r_DlyCrcEn;     // Delayed CRC enabled
424
wire [15:0] r_MaxFL;        // Maximum frame length
425
 
426
wire [15:0] r_MinFL;        // Minimum frame length
427 42 mohor
wire        ShortFrame;
428
wire        DribbleNibble;  // Extra nibble received
429
wire        ReceivedPacketTooBig; // Received packet is too big
430 15 mohor
wire [47:0] r_MAC;          // MAC address
431 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
432 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
433
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
434 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
435 15 mohor
wire  [6:0] r_IPGT;         // 
436
wire  [6:0] r_IPGR1;        // 
437
wire  [6:0] r_IPGR2;        // 
438
wire  [5:0] r_CollValid;    // 
439 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
440
wire        r_TxPauseRq;    // Transmit PAUSE request
441 15 mohor
 
442
wire  [3:0] r_MaxRet;       //
443
wire        r_NoBckof;      // 
444
wire        r_ExDfrEn;      // 
445
wire        r_TxFlow;       // Tx flow control enable
446
wire        r_IFG;          // Minimum interframe gap for incoming packets
447
 
448 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
449
wire        TxE_IRQ;        // Interrupt Tx Error
450
wire        RxB_IRQ;        // Interrupt Rx Buffer
451 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
452 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
453 15 mohor
 
454 304 tadejm
//wire        DWord;
455
wire        ByteSelected;
456 15 mohor
wire        BDAck;
457 103 mohor
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
458 304 tadejm
wire  [3:0] BDCs;           // Buffer descriptor CS
459 202 mohor
wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
460
                            // but data is not valid.
461 327 igorm
wire        r_Pad;
462
wire        r_CrcEn;
463
wire        r_FullD;
464
wire        r_Pro;
465
wire        r_Bro;
466
wire        r_NoPre;
467
wire        r_RxFlow;
468
wire        r_PassAll;
469
wire        TxCtrlEndFrm;
470
wire        StartTxDone;
471
wire        SetPauseTimer;
472
wire        TxUsedDataIn;
473
wire        TxDoneIn;
474
wire        TxAbortIn;
475
wire        PerPacketPad;
476
wire        PadOut;
477
wire        PerPacketCrcEn;
478
wire        CrcEnOut;
479
wire        TxStartFrmOut;
480
wire        TxEndFrmOut;
481
wire        ReceivedPauseFrm;
482
wire        ControlFrmAddressOK;
483
wire        RxStatusWriteLatched_sync2;
484
wire        LateCollision;
485
wire        DeferIndication;
486
wire        LateCollLatched;
487
wire        DeferLatched;
488
wire        RstDeferLatched;
489
wire        CarrierSenseLost;
490 15 mohor
 
491 103 mohor
wire        temp_wb_ack_o;
492
wire [31:0] temp_wb_dat_o;
493
wire        temp_wb_err_o;
494 15 mohor
 
495 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
496
  reg         temp_wb_ack_o_reg;
497
  reg [31:0]  temp_wb_dat_o_reg;
498
  reg         temp_wb_err_o_reg;
499
`endif
500
 
501 304 tadejm
//assign DWord = &wb_sel_i;
502
assign ByteSelected = |wb_sel_i;
503
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3];   // 0x0   - 0x3FF
504
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2];   // 0x0   - 0x3FF
505
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1];   // 0x0   - 0x3FF
506
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0];   // 0x0   - 0x3FF
507
assign BDCs[3]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[3];   // 0x400 - 0x7FF
508
assign BDCs[2]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[2];   // 0x400 - 0x7FF
509
assign BDCs[1]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[1];   // 0x400 - 0x7FF
510
assign BDCs[0]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[0];   // 0x400 - 0x7FF
511
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11];                   // 0x800 - 0xfFF
512
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
513
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
514 15 mohor
 
515 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
516
  assign wb_ack_o = temp_wb_ack_o_reg;
517
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
518
  assign wb_err_o = temp_wb_err_o_reg;
519
`else
520
  assign wb_ack_o = temp_wb_ack_o;
521
  assign wb_dat_o[31:0] = temp_wb_dat_o;
522
  assign wb_err_o = temp_wb_err_o;
523
`endif
524 15 mohor
 
525 327 igorm
`ifdef ETH_AVALON_BUS
526
  // As Avalon has no corresponding "error" signal, I (erroneously) will
527
  // send an ack to Avalon, even when accessing undefined memory. This
528
  // is a grey area in Avalon vs. Wishbone specs: My understanding
529
  // is that Avalon expects all memory addressable by the addr bus feeding
530
  // a slave to be, at the very minimum, readable.
531
  assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
532
`else // WISHBONE
533
  assign temp_wb_ack_o = (|RegCs) | BDAck;
534
`endif
535 15 mohor
 
536 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
537
  always @ (posedge wb_clk_i or posedge wb_rst_i)
538
  begin
539
    if(wb_rst_i)
540
      begin
541 352 olof
        temp_wb_ack_o_reg <= 1'b0;
542
        temp_wb_dat_o_reg <= 32'h0;
543
        temp_wb_err_o_reg <= 1'b0;
544 103 mohor
      end
545
    else
546
      begin
547 352 olof
        temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
548
        temp_wb_dat_o_reg <= temp_wb_dat_o;
549
        temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
550 103 mohor
      end
551
  end
552
`endif
553
 
554
 
555 15 mohor
// Connecting Ethernet registers
556 352 olof
eth_registers ethreg1
557 15 mohor
(
558 47 mohor
  .DataIn(wb_dat_i),                      .Address(wb_adr_i[9:2]),                    .Rw(wb_we_i),
559 17 mohor
  .Cs(RegCs),                             .Clk(wb_clk_i),                             .Reset(wb_rst_i),
560 68 mohor
  .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),
561 15 mohor
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
562 244 mohor
  .r_DlyCrcEn(r_DlyCrcEn),                .r_FullD(r_FullD),
563 15 mohor
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
564 52 billditt
  .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),
565
  .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
566 76 mohor
  .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),
567 21 mohor
  .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),
568 149 mohor
  .r_IPGT(r_IPGT),
569 15 mohor
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
570
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
571
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
572 253 mohor
  .r_MiiNoPre(r_MiiNoPre),                .r_ClkDiv(r_ClkDiv),
573 15 mohor
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
574
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
575
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
576
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
577
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
578 321 igorm
  .r_TxBDNum(r_TxBDNum),                  .int_o(int_o),
579 149 mohor
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
580
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
581
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
582 360 olof
  .dbg_dat(wb_dbg_dat0),
583 261 mohor
  .SetPauseTimer(SetPauseTimer)
584 149 mohor
 
585 15 mohor
);
586
 
587
 
588
 
589
wire  [7:0] RxData;
590
wire        RxValid;
591
wire        RxStartFrm;
592
wire        RxEndFrm;
593 41 mohor
wire        RxAbort;
594 15 mohor
 
595
wire        WillTransmit;            // Will transmit (to RxEthMAC)
596
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
597
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
598
wire        WillSendControlFrame;
599
wire        ReceiveEnd;
600
wire        ReceivedPacketGood;
601
wire        ReceivedLengthOK;
602 42 mohor
wire        InvalidSymbol;
603
wire        LatchedCrcError;
604
wire        RxLateCollision;
605 59 mohor
wire  [3:0] RetryCntLatched;
606
wire  [3:0] RetryCnt;
607
wire        StartTxAbort;
608
wire        MaxCollisionOccured;
609
wire        RetryLimit;
610
wire        StatePreamble;
611
wire  [1:0] StateData;
612 15 mohor
 
613
// Connecting MACControl
614 352 olof
eth_maccontrol maccontrol1
615 15 mohor
(
616 255 mohor
  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(TPauseRq),
617 149 mohor
  .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),
618 15 mohor
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
619
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
620 20 mohor
  .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),
621 15 mohor
  .RxData(RxData),                              .RxValid(RxValid),
622
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
623
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
624 261 mohor
  .TxFlow(r_TxFlow),
625 15 mohor
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
626
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
627
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
628 240 tadejm
  .CrcEnOut(CrcEnOut),                          .TxReset(wb_rst_i),
629
  .RxReset(wb_rst_i),                           .ReceivedLengthOK(ReceivedLengthOK),
630 15 mohor
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
631
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
632
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
633
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
634 261 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm),          .ControlFrmAddressOK(ControlFrmAddressOK),
635 272 tadejm
  .SetPauseTimer(SetPauseTimer),
636
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),                .r_PassAll(r_PassAll)
637 15 mohor
);
638
 
639
 
640
 
641
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
642
wire Collision;               // Synchronized Collision
643
 
644
reg CarrierSense_Tx1;
645
reg CarrierSense_Tx2;
646
reg Collision_Tx1;
647
reg Collision_Tx2;
648
 
649
reg RxEnSync;                 // Synchronized Receive Enable
650
reg WillTransmit_q;
651
reg WillTransmit_q2;
652
 
653
 
654
 
655
// Muxed MII receive data valid
656 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
657 15 mohor
 
658
// Muxed MII Receive Error
659 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
660 15 mohor
 
661
// Muxed MII Receive Data
662 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
663 15 mohor
 
664
 
665
 
666
// Connecting TxEthMAC
667 352 olof
eth_txethmac txethmac1
668 15 mohor
(
669 240 tadejm
  .MTxClk(mtx_clk_pad_i),             .Reset(wb_rst_i),                   .CarrierSense(TxCarrierSense),
670 15 mohor
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
671
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
672
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
673
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
674
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
675
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
676 17 mohor
  .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),
677
  .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
678 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
679 59 mohor
  .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),
680
  .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
681 276 tadejm
  .DeferIndication(DeferIndication),  .StatePreamble(StatePreamble),      .StateData(StateData)
682 15 mohor
);
683
 
684
 
685
 
686
 
687
wire  [15:0]  RxByteCnt;
688
wire          RxByteCntEq0;
689
wire          RxByteCntGreat2;
690
wire          RxByteCntMaxFrame;
691
wire          RxCrcError;
692
wire          RxStateIdle;
693
wire          RxStatePreamble;
694
wire          RxStateSFD;
695
wire   [1:0]  RxStateData;
696 250 mohor
wire          AddressMiss;
697 15 mohor
 
698
 
699
 
700
// Connecting RxEthMAC
701 352 olof
eth_rxethmac rxethmac1
702 15 mohor
(
703 21 mohor
  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
704 15 mohor
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
705 240 tadejm
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(wb_rst_i),
706 15 mohor
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
707 65 mohor
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt),
708 15 mohor
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
709
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
710 52 billditt
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
711 63 mohor
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
712 250 mohor
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort),
713 261 mohor
  .AddressMiss(AddressMiss),            .PassAll(r_PassAll),                  .ControlFrmAddressOK(ControlFrmAddressOK)
714 15 mohor
);
715
 
716
 
717
// MII Carrier Sense Synchronization
718 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
719 15 mohor
begin
720 240 tadejm
  if(wb_rst_i)
721 15 mohor
    begin
722 352 olof
      CarrierSense_Tx1 <=  1'b0;
723
      CarrierSense_Tx2 <=  1'b0;
724 15 mohor
    end
725
  else
726
    begin
727 352 olof
      CarrierSense_Tx1 <=  mcrs_pad_i;
728
      CarrierSense_Tx2 <=  CarrierSense_Tx1;
729 15 mohor
    end
730
end
731
 
732
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
733
 
734
 
735
// MII Collision Synchronization
736 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
737 15 mohor
begin
738 240 tadejm
  if(wb_rst_i)
739 15 mohor
    begin
740 352 olof
      Collision_Tx1 <=  1'b0;
741
      Collision_Tx2 <=  1'b0;
742 15 mohor
    end
743
  else
744
    begin
745 352 olof
      Collision_Tx1 <=  mcoll_pad_i;
746 15 mohor
      if(ResetCollision)
747 352 olof
        Collision_Tx2 <=  1'b0;
748 15 mohor
      else
749
      if(Collision_Tx1)
750 352 olof
        Collision_Tx2 <=  1'b1;
751 15 mohor
    end
752
end
753
 
754
 
755
// Synchronized Collision
756
assign Collision = ~r_FullD & Collision_Tx2;
757
 
758
 
759
 
760
// Delayed WillTransmit
761 20 mohor
always @ (posedge mrx_clk_pad_i)
762 15 mohor
begin
763 352 olof
  WillTransmit_q <=  WillTransmit;
764
  WillTransmit_q2 <=  WillTransmit_q;
765 15 mohor
end
766
 
767
 
768
assign Transmitting = ~r_FullD & WillTransmit_q2;
769
 
770
 
771
 
772
// Synchronized Receive Enable
773 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
774 15 mohor
begin
775 240 tadejm
  if(wb_rst_i)
776 352 olof
    RxEnSync <=  1'b0;
777 15 mohor
  else
778 301 knguyen
  if(~mrxdv_pad_i)
779 352 olof
    RxEnSync <=  r_RxEn;
780 15 mohor
end
781
 
782
 
783
 
784 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
785
always @ (posedge wb_clk_i or posedge wb_rst_i)
786
begin
787
  if(wb_rst_i)
788
    WillSendControlFrame_sync1 <= 1'b0;
789
  else
790 352 olof
    WillSendControlFrame_sync1 <= WillSendControlFrame;
791 149 mohor
end
792 15 mohor
 
793 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
794
begin
795
  if(wb_rst_i)
796
    WillSendControlFrame_sync2 <= 1'b0;
797
  else
798 352 olof
    WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
799 149 mohor
end
800
 
801
always @ (posedge wb_clk_i or posedge wb_rst_i)
802
begin
803
  if(wb_rst_i)
804
    WillSendControlFrame_sync3 <= 1'b0;
805
  else
806 352 olof
    WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
807 149 mohor
end
808
 
809
always @ (posedge wb_clk_i or posedge wb_rst_i)
810
begin
811
  if(wb_rst_i)
812
    RstTxPauseRq <= 1'b0;
813
  else
814 352 olof
    RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
815 149 mohor
end
816
 
817
 
818 255 mohor
 
819
 
820
// TX Pause request Synchronization
821
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
822
begin
823
  if(wb_rst_i)
824
    begin
825 352 olof
      TxPauseRq_sync1 <=  1'b0;
826
      TxPauseRq_sync2 <=  1'b0;
827
      TxPauseRq_sync3 <=  1'b0;
828 255 mohor
    end
829
  else
830
    begin
831 352 olof
      TxPauseRq_sync1 <=  (r_TxPauseRq & r_TxFlow);
832
      TxPauseRq_sync2 <=  TxPauseRq_sync1;
833
      TxPauseRq_sync3 <=  TxPauseRq_sync2;
834 255 mohor
    end
835
end
836
 
837
 
838
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
839
begin
840
  if(wb_rst_i)
841 352 olof
    TPauseRq <=  1'b0;
842 255 mohor
  else
843 352 olof
    TPauseRq <=  TxPauseRq_sync2 & (~TxPauseRq_sync3);
844 255 mohor
end
845
 
846
 
847 261 mohor
wire LatchedMRxErr;
848
reg RxAbort_latch;
849
reg RxAbort_sync1;
850
reg RxAbort_wb;
851
reg RxAbortRst_sync1;
852
reg RxAbortRst;
853 255 mohor
 
854 261 mohor
// Synchronizing RxAbort to the WISHBONE clock
855
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
856
begin
857
  if(wb_rst_i)
858 352 olof
    RxAbort_latch <=  1'b0;
859 261 mohor
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
860 352 olof
    RxAbort_latch <=  1'b1;
861 261 mohor
  else if(RxAbortRst)
862 352 olof
    RxAbort_latch <=  1'b0;
863 261 mohor
end
864 255 mohor
 
865 261 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
866
begin
867
  if(wb_rst_i)
868
    begin
869 352 olof
      RxAbort_sync1 <=  1'b0;
870
      RxAbort_wb    <=  1'b0;
871
      RxAbort_wb    <=  1'b0;
872 261 mohor
    end
873
  else
874
    begin
875 352 olof
      RxAbort_sync1 <=  RxAbort_latch;
876
      RxAbort_wb    <=  RxAbort_sync1;
877 261 mohor
    end
878
end
879
 
880
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
881
begin
882
  if(wb_rst_i)
883
    begin
884 352 olof
      RxAbortRst_sync1 <=  1'b0;
885
      RxAbortRst       <=  1'b0;
886 261 mohor
    end
887
  else
888
    begin
889 352 olof
      RxAbortRst_sync1 <=  RxAbort_wb;
890
      RxAbortRst       <=  RxAbortRst_sync1;
891 261 mohor
    end
892
end
893
 
894
 
895
 
896 114 mohor
// Connecting Wishbone module
897 352 olof
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH),
898 349 olof
               .TX_FIFO_DEPTH     (TX_FIFO_DEPTH),
899
               .TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH),
900
               .RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH),
901
               .RX_FIFO_DEPTH     (RX_FIFO_DEPTH),
902
               .RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH))
903
wishbone
904 15 mohor
(
905 41 mohor
  .WB_CLK_I(wb_clk_i),                .WB_DAT_I(wb_dat_i),
906 103 mohor
  .WB_DAT_O(BD_WB_DAT_O),
907 15 mohor
 
908
  // WISHBONE slave
909 76 mohor
  .WB_ADR_I(wb_adr_i[9:2]),           .WB_WE_I(wb_we_i),
910 21 mohor
  .BDCs(BDCs),                        .WB_ACK_O(BDAck),
911 15 mohor
 
912 240 tadejm
  .Reset(wb_rst_i),
913 41 mohor
 
914
  // WISHBONE master
915 327 igorm
  .m_wb_adr_o(m_wb_adr_tmp),          .m_wb_sel_o(m_wb_sel_o),                  .m_wb_we_o(m_wb_we_o),
916 41 mohor
  .m_wb_dat_i(m_wb_dat_i),            .m_wb_dat_o(m_wb_dat_o),                  .m_wb_cyc_o(m_wb_cyc_o),
917
  .m_wb_stb_o(m_wb_stb_o),            .m_wb_ack_i(m_wb_ack_i),                  .m_wb_err_i(m_wb_err_i),
918 214 mohor
 
919
`ifdef ETH_WISHBONE_B3
920
  .m_wb_cti_o(m_wb_cti_o),            .m_wb_bte_o(m_wb_bte_o),
921
`endif
922
 
923 41 mohor
 
924 15 mohor
    //TX
925 21 mohor
  .MTxClk(mtx_clk_pad_i),             .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
926 59 mohor
  .TxUsedData(TxUsedData),            .TxData(TxData),
927 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
928 149 mohor
  .TxDone(TxDone),
929
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
930 15 mohor
 
931
  // Register
932 34 mohor
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
933 321 igorm
  .r_RxFlow(r_RxFlow),                      .r_PassAll(r_PassAll),
934 15 mohor
 
935
  //RX
936 21 mohor
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
937 41 mohor
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
938 76 mohor
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
939 149 mohor
  .TxE_IRQ(TxE_IRQ),                  .TxB_IRQ(TxB_IRQ),
940 21 mohor
 
941 272 tadejm
  .RxAbort(RxAbort_wb),               .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
942 41 mohor
 
943 42 mohor
  .InvalidSymbol(InvalidSymbol),      .LatchedCrcError(LatchedCrcError),        .RxLength(RxByteCnt),
944
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
945 59 mohor
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
946
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
947 327 igorm
  .RstDeferLatched(RstDeferLatched),
948 261 mohor
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss),
949
  .ReceivedPauseFrm(ReceivedPauseFrm)
950 59 mohor
 
951 210 mohor
`ifdef ETH_BIST
952 218 mohor
  ,
953 302 markom
  .mbist_si_i       (mbist_si_i),
954
  .mbist_so_o       (mbist_so_o),
955
  .mbist_ctrl_i       (mbist_ctrl_i)
956 210 mohor
`endif
957 360 olof
`ifdef WISHBONE_DEBUG
958
  ,
959
  .dbg_dat0(wb_dbg_dat0)
960
`endif
961
 
962 15 mohor
);
963
 
964 327 igorm
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
965 15 mohor
 
966
// Connecting MacStatus module
967 352 olof
eth_macstatus macstatus1
968 15 mohor
(
969 240 tadejm
  .MRxClk(mrx_clk_pad_i),             .Reset(wb_rst_i),
970 42 mohor
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK),
971
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb),
972
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble),
973
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt),
974
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame),
975 261 mohor
  .InvalidSymbol(InvalidSymbol),
976 42 mohor
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
977
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
978
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
979
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
980 59 mohor
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
981
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
982
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
983 276 tadejm
  .LateCollLatched(LateCollLatched),  .DeferIndication(DeferIndication),           .DeferLatched(DeferLatched),
984 327 igorm
  .RstDeferLatched(RstDeferLatched),
985 59 mohor
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
986 125 mohor
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
987 168 mohor
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
988 15 mohor
);
989
 
990
 
991
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.