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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Blame information for rev 365

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3 364 olof
////  ethmac.v                                                    ////
4 15 mohor
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41 364 olof
// 2011-08-09 olof@opencores.org
42
// Renamed from eth_top.v to ethmac.v to better fit into the OpenCores
43
// Structure
44
//
45 15 mohor
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48 333 igorm
// Revision 1.51  2005/02/21 11:13:17  igorm
49
// Defer indication fixed.
50
//
51 327 igorm
// Revision 1.50  2004/04/26 15:26:23  igorm
52
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
53
//   previous update of the core.
54
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
55
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
56
//   register. (thanks to Mathias and Torbjorn)
57
// - Multicast reception was fixed. Thanks to Ulrich Gries
58
//
59 321 igorm
// Revision 1.49  2003/11/12 18:24:59  tadejm
60
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
61
//
62 304 tadejm
// Revision 1.48  2003/10/17 07:46:16  markom
63
// mbist signals updated according to newest convention
64
//
65 302 markom
// Revision 1.47  2003/10/06 15:43:45  knguyen
66
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
67
//
68 301 knguyen
// Revision 1.46  2003/01/30 13:30:22  tadejm
69
// Defer indication changed.
70
//
71 276 tadejm
// Revision 1.45  2003/01/22 13:49:26  tadejm
72
// When control packets were received, they were ignored in some cases.
73
//
74 272 tadejm
// Revision 1.44  2003/01/21 12:09:40  mohor
75
// When receiving normal data frame and RxFlow control was switched on, RXB
76
// interrupt was not set.
77
//
78 270 mohor
// Revision 1.43  2002/11/22 01:57:06  mohor
79
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
80
// synchronized.
81
//
82 261 mohor
// Revision 1.42  2002/11/21 00:09:19  mohor
83
// TPauseRq synchronized to tx_clk.
84
//
85 255 mohor
// Revision 1.41  2002/11/19 18:13:49  mohor
86
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
87
//
88 253 mohor
// Revision 1.40  2002/11/19 17:34:25  mohor
89
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
90
// that a frame was received because of the promiscous mode.
91
//
92 250 mohor
// Revision 1.39  2002/11/18 17:31:55  mohor
93
// wb_rst_i is used for MIIM reset.
94
//
95 248 mohor
// Revision 1.38  2002/11/14 18:37:20  mohor
96
// r_Rst signal does not reset any module any more and is removed from the design.
97
//
98 244 mohor
// Revision 1.37  2002/11/13 22:25:36  tadejm
99
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
100
//
101 240 tadejm
// Revision 1.36  2002/10/18 17:04:20  tadejm
102
// Changed BIST scan signals.
103
//
104 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
105
// Typo error fixed. (When using Bist)
106
//
107 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
108
// Signals for WISHBONE B3 compliant interface added.
109
//
110 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
111
// BIST added.
112
//
113 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
114
// CsMiss added. When address between 0x800 and 0xfff is accessed within
115
// Ethernet Core, error acknowledge is generated.
116
//
117 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
118
// CarrierSenseLost bug fixed when operating in full duplex mode.
119
//
120 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
121
// Ethernet debug registers removed.
122
//
123 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
124
// Error acknowledge is generated when accessing BDs and RST bit in the
125
// MODER register (r_Rst) is set.
126
//
127 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
128
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
129
// connected.
130
//
131 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
132
// RxAbort changed. Packets received with MRxErr (from PHY) are also
133
// aborted.
134
//
135 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
136
// EXTERNAL_DMA removed. External DMA not supported.
137
//
138 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
139
// Outputs registered. Reset changed for eth_wishbone module.
140
//
141 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
142
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
143
// selected in eth_defines.v
144
//
145 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
146
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
147
// name was incorrect.
148
//
149 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
150
// Small fixes for external/internal DMA missmatches.
151
//
152 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
153
// Interrupts changed in the top file
154
//
155 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
156
// Small fixes.
157
//
158 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
159
// Registered trimmed. Unused registers removed.
160
//
161 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
162
// EXTERNAL_DMA used instead of WISHBONE_DMA.
163
//
164 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
165
// Testbench fixed, code simplified, unused signals removed.
166
//
167 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
168
// RxAbort is connected differently.
169
//
170 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
171
// Changes that were lost when updating from 1.11 to 1.14 fixed.
172
//
173 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
174
// Modified for Address Checking,
175
// addition of eth_addrcheck.v
176
//
177
// Revision 1.13  2002/02/12 17:03:03  mohor
178
// HASH0 and HASH1 registers added. Registers address width was
179
// changed to 8 bits.
180
//
181
// Revision 1.12  2002/02/11 09:18:22  mohor
182
// Tx status is written back to the BD.
183
//
184 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
185
// Rx status is written back to the BD.
186
//
187 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
188
// non-DMA host interface added. Select the right configutation in eth_defines.
189
//
190 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
191
// Link in the header changed.
192
//
193 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
194
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
195
// instead of the number of RX descriptors).
196
//
197 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
198
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
199
//
200 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
201
// Number of addresses (wb_adr_i) minimized.
202
//
203 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
204
// eth_timescale.v changed to timescale.v This is done because of the
205
// simulation of the few cores in a one joined project.
206
//
207 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
208
// Status signals changed, Adress decoding changed, interrupt controller
209
// added.
210
//
211 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
212
// Defines changed (All precede with ETH_). Small changes because some
213
// tools generate warnings when two operands are together. Synchronization
214
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
215
// demands).
216
//
217 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
218
// Signal names changed on the top level for easier pad insertion (ASIC).
219
//
220 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
221
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
222
// Include files fixed to contain no path.
223
// File names and module names changed ta have a eth_ prologue in the name.
224
// File eth_timescale.v is used to define timescale
225
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
226
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
227
// and Mdo_OE. The bidirectional signal must be created on the top level. This
228
// is done due to the ASIC tools.
229
//
230 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
231
// Unconnected signals are now connected.
232
//
233
// Revision 1.1  2001/07/30 21:23:42  mohor
234
// Directory structure changed. Files checked and joind together.
235
//
236
//
237
//
238 20 mohor
// 
239 15 mohor
 
240
 
241 356 olof
`include "ethmac_defines.v"
242 22 mohor
`include "timescale.v"
243 15 mohor
 
244
 
245 364 olof
module ethmac
246 15 mohor
(
247
  // WISHBONE common
248 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
249 15 mohor
 
250
  // WISHBONE slave
251 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
252 15 mohor
 
253 41 mohor
  // WISHBONE master
254
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
255
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
256
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
257
 
258 214 mohor
`ifdef ETH_WISHBONE_B3
259
  m_wb_cti_o, m_wb_bte_o,
260
`endif
261
 
262 15 mohor
  //TX
263 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
264 15 mohor
 
265
  //RX
266 365 olof
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
267 15 mohor
 
268
  // MIIM
269 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
270 17 mohor
 
271 21 mohor
  int_o
272 17 mohor
 
273 210 mohor
  // Bist
274
`ifdef ETH_BIST
275 227 tadejm
  ,
276
  // debug chain signals
277 302 markom
  mbist_si_i,       // bist scan serial in
278
  mbist_so_o,       // bist scan serial out
279
  mbist_ctrl_i        // bist chain shift control
280 210 mohor
`endif
281 21 mohor
 
282 15 mohor
);
283
 
284
 
285 349 olof
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
286
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
287
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
288
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
289
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
290
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
291 15 mohor
 
292
 
293
// WISHBONE common
294 17 mohor
input           wb_clk_i;     // WISHBONE clock
295
input           wb_rst_i;     // WISHBONE reset
296
input   [31:0]  wb_dat_i;     // WISHBONE data input
297
output  [31:0]  wb_dat_o;     // WISHBONE data output
298
output          wb_err_o;     // WISHBONE error output
299 15 mohor
 
300
// WISHBONE slave
301 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
302 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
303
input           wb_we_i;      // WISHBONE write enable input
304
input           wb_cyc_i;     // WISHBONE cycle input
305
input           wb_stb_i;     // WISHBONE strobe input
306
output          wb_ack_o;     // WISHBONE acknowledge output
307 15 mohor
 
308 41 mohor
// WISHBONE master
309
output  [31:0]  m_wb_adr_o;
310
output   [3:0]  m_wb_sel_o;
311
output          m_wb_we_o;
312
input   [31:0]  m_wb_dat_i;
313
output  [31:0]  m_wb_dat_o;
314
output          m_wb_cyc_o;
315
output          m_wb_stb_o;
316
input           m_wb_ack_i;
317
input           m_wb_err_i;
318 15 mohor
 
319 327 igorm
wire    [29:0]  m_wb_adr_tmp;
320
 
321 214 mohor
`ifdef ETH_WISHBONE_B3
322
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
323
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
324
`endif
325 41 mohor
 
326 15 mohor
// Tx
327 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
328 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
329
output          mtxen_pad_o;   // Transmit enable (to PHY)
330
output          mtxerr_pad_o;  // Transmit error (to PHY)
331 15 mohor
 
332
// Rx
333 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
334 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
335
input           mrxdv_pad_i;   // Receive data valid (from PHY)
336
input           mrxerr_pad_i;  // Receive data error (from PHY)
337 15 mohor
 
338
// Common Tx and Rx
339 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
340
input           mcrs_pad_i;    // Carrier sense (from PHY)
341 15 mohor
 
342
// MII Management interface
343 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
344
output          mdc_pad_o;     // MII Management data clock (to PHY)
345
output          md_pad_o;      // MII data output (to I/O cell)
346 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
347 15 mohor
 
348 21 mohor
output          int_o;         // Interrupt output
349 15 mohor
 
350 210 mohor
// Bist
351
`ifdef ETH_BIST
352 302 markom
input   mbist_si_i;       // bist scan serial in
353
output  mbist_so_o;       // bist scan serial out
354
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
355 210 mohor
`endif
356
 
357 360 olof
wire    [31:0]  wb_dbg_dat0;
358
 
359 15 mohor
wire     [7:0]  r_ClkDiv;
360
wire            r_MiiNoPre;
361
wire    [15:0]  r_CtrlData;
362
wire     [4:0]  r_FIAD;
363
wire     [4:0]  r_RGAD;
364
wire            r_WCtrlData;
365
wire            r_RStat;
366
wire            r_ScanStat;
367
wire            NValid_stat;
368
wire            Busy_stat;
369
wire            LinkFail;
370
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
371
wire            WCtrlDataStart;
372
wire            RStatStart;
373
wire            UpdateMIIRX_DATAReg;
374
 
375
wire            TxStartFrm;
376
wire            TxEndFrm;
377
wire            TxUsedData;
378
wire     [7:0]  TxData;
379
wire            TxRetry;
380
wire            TxAbort;
381
wire            TxUnderRun;
382
wire            TxDone;
383
 
384
 
385 149 mohor
reg             WillSendControlFrame_sync1;
386
reg             WillSendControlFrame_sync2;
387
reg             WillSendControlFrame_sync3;
388
reg             RstTxPauseRq;
389 15 mohor
 
390 255 mohor
reg             TxPauseRq_sync1;
391
reg             TxPauseRq_sync2;
392
reg             TxPauseRq_sync3;
393
reg             TPauseRq;
394 15 mohor
 
395 255 mohor
 
396 15 mohor
// Connecting Miim module
397 352 olof
eth_miim miim1
398 15 mohor
(
399 365 olof
  .Clk(wb_clk_i),
400
  .Reset(wb_rst_i),
401
  .Divider(r_ClkDiv),
402
  .NoPre(r_MiiNoPre),
403
  .CtrlData(r_CtrlData),
404
  .Rgad(r_RGAD),
405
  .Fiad(r_FIAD),
406
  .WCtrlData(r_WCtrlData),
407
  .RStat(r_RStat),
408
  .ScanStat(r_ScanStat),
409
  .Mdi(md_pad_i),
410
  .Mdo(md_pad_o),
411
  .MdoEn(md_padoe_o),
412
  .Mdc(mdc_pad_o),
413
  .Busy(Busy_stat),
414
  .Prsd(Prsd),
415
  .LinkFail(LinkFail),
416
  .Nvalid(NValid_stat),
417
  .WCtrlDataStart(WCtrlDataStart),
418
  .RStatStart(RStatStart),
419
  .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
420 15 mohor
);
421
 
422
 
423
 
424
 
425 304 tadejm
wire  [3:0] RegCs;          // Connected to registers
426 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
427 42 mohor
wire        r_RecSmall;     // Receive small frames
428 15 mohor
wire        r_LoopBck;      // Loopback
429
wire        r_TxEn;         // Tx Enable
430
wire        r_RxEn;         // Rx Enable
431
 
432
wire        MRxDV_Lb;       // Muxed MII receive data valid
433
wire        MRxErr_Lb;      // Muxed MII Receive Error
434
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
435
wire        Transmitting;   // Indication that TxEthMAC is transmitting
436
wire        r_HugEn;        // Huge packet enable
437
wire        r_DlyCrcEn;     // Delayed CRC enabled
438
wire [15:0] r_MaxFL;        // Maximum frame length
439
 
440
wire [15:0] r_MinFL;        // Minimum frame length
441 42 mohor
wire        ShortFrame;
442
wire        DribbleNibble;  // Extra nibble received
443
wire        ReceivedPacketTooBig; // Received packet is too big
444 15 mohor
wire [47:0] r_MAC;          // MAC address
445 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
446 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
447
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
448 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
449 15 mohor
wire  [6:0] r_IPGT;         // 
450
wire  [6:0] r_IPGR1;        // 
451
wire  [6:0] r_IPGR2;        // 
452
wire  [5:0] r_CollValid;    // 
453 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
454
wire        r_TxPauseRq;    // Transmit PAUSE request
455 15 mohor
 
456
wire  [3:0] r_MaxRet;       //
457
wire        r_NoBckof;      // 
458
wire        r_ExDfrEn;      // 
459
wire        r_TxFlow;       // Tx flow control enable
460
wire        r_IFG;          // Minimum interframe gap for incoming packets
461
 
462 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
463
wire        TxE_IRQ;        // Interrupt Tx Error
464
wire        RxB_IRQ;        // Interrupt Rx Buffer
465 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
466 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
467 15 mohor
 
468 304 tadejm
//wire        DWord;
469
wire        ByteSelected;
470 15 mohor
wire        BDAck;
471 365 olof
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module
472
                            //(for buffer descriptors read/write)
473 304 tadejm
wire  [3:0] BDCs;           // Buffer descriptor CS
474 365 olof
wire        CsMiss;         // When access to the address between 0x800
475
                            // and 0xfff occurs, acknowledge is set
476 202 mohor
                            // but data is not valid.
477 327 igorm
wire        r_Pad;
478
wire        r_CrcEn;
479
wire        r_FullD;
480
wire        r_Pro;
481
wire        r_Bro;
482
wire        r_NoPre;
483
wire        r_RxFlow;
484
wire        r_PassAll;
485
wire        TxCtrlEndFrm;
486
wire        StartTxDone;
487
wire        SetPauseTimer;
488
wire        TxUsedDataIn;
489
wire        TxDoneIn;
490
wire        TxAbortIn;
491
wire        PerPacketPad;
492
wire        PadOut;
493
wire        PerPacketCrcEn;
494
wire        CrcEnOut;
495
wire        TxStartFrmOut;
496
wire        TxEndFrmOut;
497
wire        ReceivedPauseFrm;
498
wire        ControlFrmAddressOK;
499
wire        RxStatusWriteLatched_sync2;
500
wire        LateCollision;
501
wire        DeferIndication;
502
wire        LateCollLatched;
503
wire        DeferLatched;
504
wire        RstDeferLatched;
505
wire        CarrierSenseLost;
506 15 mohor
 
507 103 mohor
wire        temp_wb_ack_o;
508
wire [31:0] temp_wb_dat_o;
509
wire        temp_wb_err_o;
510 15 mohor
 
511 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
512
  reg         temp_wb_ack_o_reg;
513
  reg [31:0]  temp_wb_dat_o_reg;
514
  reg         temp_wb_err_o_reg;
515
`endif
516
 
517 304 tadejm
//assign DWord = &wb_sel_i;
518
assign ByteSelected = |wb_sel_i;
519
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3];   // 0x0   - 0x3FF
520
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2];   // 0x0   - 0x3FF
521
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1];   // 0x0   - 0x3FF
522
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0];   // 0x0   - 0x3FF
523
assign BDCs[3]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[3];   // 0x400 - 0x7FF
524
assign BDCs[2]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[2];   // 0x400 - 0x7FF
525
assign BDCs[1]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[1];   // 0x400 - 0x7FF
526
assign BDCs[0]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[0];   // 0x400 - 0x7FF
527
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11];                   // 0x800 - 0xfFF
528
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
529
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
530 15 mohor
 
531 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
532
  assign wb_ack_o = temp_wb_ack_o_reg;
533
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
534
  assign wb_err_o = temp_wb_err_o_reg;
535
`else
536
  assign wb_ack_o = temp_wb_ack_o;
537
  assign wb_dat_o[31:0] = temp_wb_dat_o;
538
  assign wb_err_o = temp_wb_err_o;
539
`endif
540 15 mohor
 
541 327 igorm
`ifdef ETH_AVALON_BUS
542
  // As Avalon has no corresponding "error" signal, I (erroneously) will
543
  // send an ack to Avalon, even when accessing undefined memory. This
544
  // is a grey area in Avalon vs. Wishbone specs: My understanding
545
  // is that Avalon expects all memory addressable by the addr bus feeding
546
  // a slave to be, at the very minimum, readable.
547
  assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
548
`else // WISHBONE
549
  assign temp_wb_ack_o = (|RegCs) | BDAck;
550
`endif
551 15 mohor
 
552 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
553
  always @ (posedge wb_clk_i or posedge wb_rst_i)
554
  begin
555
    if(wb_rst_i)
556
      begin
557 352 olof
        temp_wb_ack_o_reg <= 1'b0;
558
        temp_wb_dat_o_reg <= 32'h0;
559
        temp_wb_err_o_reg <= 1'b0;
560 103 mohor
      end
561
    else
562
      begin
563 352 olof
        temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
564
        temp_wb_dat_o_reg <= temp_wb_dat_o;
565
        temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
566 103 mohor
      end
567
  end
568
`endif
569
 
570
 
571 15 mohor
// Connecting Ethernet registers
572 352 olof
eth_registers ethreg1
573 15 mohor
(
574 365 olof
  .DataIn(wb_dat_i),
575
  .Address(wb_adr_i[9:2]),
576
  .Rw(wb_we_i),
577
  .Cs(RegCs),
578
  .Clk(wb_clk_i),
579
  .Reset(wb_rst_i),
580
  .DataOut(RegDataOut),
581
  .r_RecSmall(r_RecSmall),
582
  .r_Pad(r_Pad),
583
  .r_HugEn(r_HugEn),
584
  .r_CrcEn(r_CrcEn),
585
  .r_DlyCrcEn(r_DlyCrcEn),
586
  .r_FullD(r_FullD),
587
  .r_ExDfrEn(r_ExDfrEn),
588
  .r_NoBckof(r_NoBckof),
589
  .r_LoopBck(r_LoopBck),
590
  .r_IFG(r_IFG),
591
  .r_Pro(r_Pro),
592
  .r_Iam(),
593
  .r_Bro(r_Bro),
594
  .r_NoPre(r_NoPre),
595
  .r_TxEn(r_TxEn),
596
  .r_RxEn(r_RxEn),
597
  .Busy_IRQ(Busy_IRQ),
598
  .RxE_IRQ(RxE_IRQ),
599
  .RxB_IRQ(RxB_IRQ),
600
  .TxE_IRQ(TxE_IRQ),
601
  .TxB_IRQ(TxB_IRQ),
602
  .r_IPGT(r_IPGT),
603
  .r_IPGR1(r_IPGR1),
604
  .r_IPGR2(r_IPGR2),
605
  .r_MinFL(r_MinFL),
606
  .r_MaxFL(r_MaxFL),
607
  .r_MaxRet(r_MaxRet),
608
  .r_CollValid(r_CollValid),
609
  .r_TxFlow(r_TxFlow),
610
  .r_RxFlow(r_RxFlow),
611
  .r_PassAll(r_PassAll),
612
  .r_MiiNoPre(r_MiiNoPre),
613
  .r_ClkDiv(r_ClkDiv),
614
  .r_WCtrlData(r_WCtrlData),
615
  .r_RStat(r_RStat),
616
  .r_ScanStat(r_ScanStat),
617
  .r_RGAD(r_RGAD),
618
  .r_FIAD(r_FIAD),
619
  .r_CtrlData(r_CtrlData),
620
  .NValid_stat(NValid_stat),
621
  .Busy_stat(Busy_stat),
622
  .LinkFail(LinkFail),
623
  .r_MAC(r_MAC),
624
  .WCtrlDataStart(WCtrlDataStart),
625
  .RStatStart(RStatStart),
626
  .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),
627
  .Prsd(Prsd),
628
  .r_TxBDNum(r_TxBDNum),
629
  .int_o(int_o),
630
  .r_HASH0(r_HASH0),
631
  .r_HASH1(r_HASH1),
632
  .r_TxPauseRq(r_TxPauseRq),
633
  .r_TxPauseTV(r_TxPauseTV),
634
  .RstTxPauseRq(RstTxPauseRq),
635
  .TxCtrlEndFrm(TxCtrlEndFrm),
636
  .StartTxDone(StartTxDone),
637
  .TxClk(mtx_clk_pad_i),
638
  .RxClk(mrx_clk_pad_i),
639 360 olof
  .dbg_dat(wb_dbg_dat0),
640 261 mohor
  .SetPauseTimer(SetPauseTimer)
641 149 mohor
 
642 15 mohor
);
643
 
644
 
645
 
646
wire  [7:0] RxData;
647
wire        RxValid;
648
wire        RxStartFrm;
649
wire        RxEndFrm;
650 41 mohor
wire        RxAbort;
651 15 mohor
 
652
wire        WillTransmit;            // Will transmit (to RxEthMAC)
653 365 olof
wire        ResetCollision;          // Reset Collision (for synchronizing 
654
                                     // collision)
655 15 mohor
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
656
wire        WillSendControlFrame;
657
wire        ReceiveEnd;
658
wire        ReceivedPacketGood;
659
wire        ReceivedLengthOK;
660 42 mohor
wire        InvalidSymbol;
661
wire        LatchedCrcError;
662
wire        RxLateCollision;
663 59 mohor
wire  [3:0] RetryCntLatched;
664
wire  [3:0] RetryCnt;
665
wire        StartTxAbort;
666
wire        MaxCollisionOccured;
667
wire        RetryLimit;
668
wire        StatePreamble;
669
wire  [1:0] StateData;
670 15 mohor
 
671
// Connecting MACControl
672 352 olof
eth_maccontrol maccontrol1
673 15 mohor
(
674 365 olof
  .MTxClk(mtx_clk_pad_i),
675
  .TPauseRq(TPauseRq),
676
  .TxPauseTV(r_TxPauseTV),
677
  .TxDataIn(TxData),
678
  .TxStartFrmIn(TxStartFrm),
679
  .TxEndFrmIn(TxEndFrm),
680
  .TxUsedDataIn(TxUsedDataIn),
681
  .TxDoneIn(TxDoneIn),
682
  .TxAbortIn(TxAbortIn),
683
  .MRxClk(mrx_clk_pad_i),
684
  .RxData(RxData),
685
  .RxValid(RxValid),
686
  .RxStartFrm(RxStartFrm),
687
  .RxEndFrm(RxEndFrm),
688
  .ReceiveEnd(ReceiveEnd),
689
  .ReceivedPacketGood(ReceivedPacketGood),
690
  .TxFlow(r_TxFlow),
691
  .RxFlow(r_RxFlow),
692
  .DlyCrcEn(r_DlyCrcEn),
693
  .MAC(r_MAC),
694
  .PadIn(r_Pad | PerPacketPad),
695
  .PadOut(PadOut),
696
  .CrcEnIn(r_CrcEn | PerPacketCrcEn),
697
  .CrcEnOut(CrcEnOut),
698
  .TxReset(wb_rst_i),
699
  .RxReset(wb_rst_i),
700
  .ReceivedLengthOK(ReceivedLengthOK),
701
  .TxDataOut(TxDataOut),
702
  .TxStartFrmOut(TxStartFrmOut),
703
  .TxEndFrmOut(TxEndFrmOut),
704
  .TxUsedDataOut(TxUsedData),
705
  .TxDoneOut(TxDone),
706
  .TxAbortOut(TxAbort),
707
  .WillSendControlFrame(WillSendControlFrame),
708
  .TxCtrlEndFrm(TxCtrlEndFrm),
709
  .ReceivedPauseFrm(ReceivedPauseFrm),
710
  .ControlFrmAddressOK(ControlFrmAddressOK),
711 272 tadejm
  .SetPauseTimer(SetPauseTimer),
712 365 olof
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
713
  .r_PassAll(r_PassAll)
714 15 mohor
);
715
 
716
 
717
 
718
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
719
wire Collision;               // Synchronized Collision
720
 
721
reg CarrierSense_Tx1;
722
reg CarrierSense_Tx2;
723
reg Collision_Tx1;
724
reg Collision_Tx2;
725
 
726
reg RxEnSync;                 // Synchronized Receive Enable
727
reg WillTransmit_q;
728
reg WillTransmit_q2;
729
 
730
 
731
 
732
// Muxed MII receive data valid
733 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
734 15 mohor
 
735
// Muxed MII Receive Error
736 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
737 15 mohor
 
738
// Muxed MII Receive Data
739 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
740 15 mohor
 
741
 
742
 
743
// Connecting TxEthMAC
744 352 olof
eth_txethmac txethmac1
745 15 mohor
(
746 365 olof
  .MTxClk(mtx_clk_pad_i),
747
  .Reset(wb_rst_i),
748
  .CarrierSense(TxCarrierSense),
749
  .Collision(Collision),
750
  .TxData(TxDataOut),
751
  .TxStartFrm(TxStartFrmOut),
752
  .TxUnderRun(TxUnderRun),
753
  .TxEndFrm(TxEndFrmOut),
754
  .Pad(PadOut),
755
  .MinFL(r_MinFL),
756
  .CrcEn(CrcEnOut),
757
  .FullD(r_FullD),
758
  .HugEn(r_HugEn),
759
  .DlyCrcEn(r_DlyCrcEn),
760
  .IPGT(r_IPGT),
761
  .IPGR1(r_IPGR1),
762
  .IPGR2(r_IPGR2),
763
  .CollValid(r_CollValid),
764
  .MaxRet(r_MaxRet),
765
  .NoBckof(r_NoBckof),
766
  .ExDfrEn(r_ExDfrEn),
767
  .MaxFL(r_MaxFL),
768
  .MTxEn(mtxen_pad_o),
769
  .MTxD(mtxd_pad_o),
770
  .MTxErr(mtxerr_pad_o),
771
  .TxUsedData(TxUsedDataIn),
772
  .TxDone(TxDoneIn),
773
  .TxRetry(TxRetry),
774
  .TxAbort(TxAbortIn),
775
  .WillTransmit(WillTransmit),
776
  .ResetCollision(ResetCollision),
777
  .RetryCnt(RetryCnt),
778
  .StartTxDone(StartTxDone),
779
  .StartTxAbort(StartTxAbort),
780
  .MaxCollisionOccured(MaxCollisionOccured),
781
  .LateCollision(LateCollision),
782
  .DeferIndication(DeferIndication),
783
  .StatePreamble(StatePreamble),
784
  .StateData(StateData)
785 15 mohor
);
786
 
787
 
788
 
789
 
790
wire  [15:0]  RxByteCnt;
791
wire          RxByteCntEq0;
792
wire          RxByteCntGreat2;
793
wire          RxByteCntMaxFrame;
794
wire          RxCrcError;
795
wire          RxStateIdle;
796
wire          RxStatePreamble;
797
wire          RxStateSFD;
798
wire   [1:0]  RxStateData;
799 250 mohor
wire          AddressMiss;
800 15 mohor
 
801
 
802
 
803
// Connecting RxEthMAC
804 352 olof
eth_rxethmac rxethmac1
805 15 mohor
(
806 365 olof
  .MRxClk(mrx_clk_pad_i),
807
  .MRxDV(MRxDV_Lb),
808
  .MRxD(MRxD_Lb),
809
  .Transmitting(Transmitting),
810
  .HugEn(r_HugEn),
811
  .DlyCrcEn(r_DlyCrcEn),
812
  .MaxFL(r_MaxFL),
813
  .r_IFG(r_IFG),
814
  .Reset(wb_rst_i),
815
  .RxData(RxData),
816
  .RxValid(RxValid),
817
  .RxStartFrm(RxStartFrm),
818
  .RxEndFrm(RxEndFrm),
819
  .ByteCnt(RxByteCnt),
820
  .ByteCntEq0(RxByteCntEq0),
821
  .ByteCntGreat2(RxByteCntGreat2),
822
  .ByteCntMaxFrame(RxByteCntMaxFrame),
823
  .CrcError(RxCrcError),
824
  .StateIdle(RxStateIdle),
825
  .StatePreamble(RxStatePreamble),
826
  .StateSFD(RxStateSFD),
827
  .StateData(RxStateData),
828
  .MAC(r_MAC),
829
  .r_Pro(r_Pro),
830
  .r_Bro(r_Bro),
831
  .r_HASH0(r_HASH0),
832
  .r_HASH1(r_HASH1),
833
  .RxAbort(RxAbort),
834
  .AddressMiss(AddressMiss),
835
  .PassAll(r_PassAll),
836
  .ControlFrmAddressOK(ControlFrmAddressOK)
837 15 mohor
);
838
 
839
 
840
// MII Carrier Sense Synchronization
841 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
842 15 mohor
begin
843 240 tadejm
  if(wb_rst_i)
844 15 mohor
    begin
845 352 olof
      CarrierSense_Tx1 <=  1'b0;
846
      CarrierSense_Tx2 <=  1'b0;
847 15 mohor
    end
848
  else
849
    begin
850 352 olof
      CarrierSense_Tx1 <=  mcrs_pad_i;
851
      CarrierSense_Tx2 <=  CarrierSense_Tx1;
852 15 mohor
    end
853
end
854
 
855
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
856
 
857
 
858
// MII Collision Synchronization
859 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
860 15 mohor
begin
861 240 tadejm
  if(wb_rst_i)
862 15 mohor
    begin
863 352 olof
      Collision_Tx1 <=  1'b0;
864
      Collision_Tx2 <=  1'b0;
865 15 mohor
    end
866
  else
867
    begin
868 352 olof
      Collision_Tx1 <=  mcoll_pad_i;
869 15 mohor
      if(ResetCollision)
870 352 olof
        Collision_Tx2 <=  1'b0;
871 15 mohor
      else
872
      if(Collision_Tx1)
873 352 olof
        Collision_Tx2 <=  1'b1;
874 15 mohor
    end
875
end
876
 
877
 
878
// Synchronized Collision
879
assign Collision = ~r_FullD & Collision_Tx2;
880
 
881
 
882
 
883
// Delayed WillTransmit
884 20 mohor
always @ (posedge mrx_clk_pad_i)
885 15 mohor
begin
886 352 olof
  WillTransmit_q <=  WillTransmit;
887
  WillTransmit_q2 <=  WillTransmit_q;
888 15 mohor
end
889
 
890
 
891
assign Transmitting = ~r_FullD & WillTransmit_q2;
892
 
893
 
894
 
895
// Synchronized Receive Enable
896 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
897 15 mohor
begin
898 240 tadejm
  if(wb_rst_i)
899 352 olof
    RxEnSync <=  1'b0;
900 15 mohor
  else
901 301 knguyen
  if(~mrxdv_pad_i)
902 352 olof
    RxEnSync <=  r_RxEn;
903 15 mohor
end
904
 
905
 
906
 
907 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
908
always @ (posedge wb_clk_i or posedge wb_rst_i)
909
begin
910
  if(wb_rst_i)
911
    WillSendControlFrame_sync1 <= 1'b0;
912
  else
913 352 olof
    WillSendControlFrame_sync1 <= WillSendControlFrame;
914 149 mohor
end
915 15 mohor
 
916 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
917
begin
918
  if(wb_rst_i)
919
    WillSendControlFrame_sync2 <= 1'b0;
920
  else
921 352 olof
    WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
922 149 mohor
end
923
 
924
always @ (posedge wb_clk_i or posedge wb_rst_i)
925
begin
926
  if(wb_rst_i)
927
    WillSendControlFrame_sync3 <= 1'b0;
928
  else
929 352 olof
    WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
930 149 mohor
end
931
 
932
always @ (posedge wb_clk_i or posedge wb_rst_i)
933
begin
934
  if(wb_rst_i)
935
    RstTxPauseRq <= 1'b0;
936
  else
937 352 olof
    RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
938 149 mohor
end
939
 
940
 
941 255 mohor
 
942
 
943
// TX Pause request Synchronization
944
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
945
begin
946
  if(wb_rst_i)
947
    begin
948 352 olof
      TxPauseRq_sync1 <=  1'b0;
949
      TxPauseRq_sync2 <=  1'b0;
950
      TxPauseRq_sync3 <=  1'b0;
951 255 mohor
    end
952
  else
953
    begin
954 352 olof
      TxPauseRq_sync1 <=  (r_TxPauseRq & r_TxFlow);
955
      TxPauseRq_sync2 <=  TxPauseRq_sync1;
956
      TxPauseRq_sync3 <=  TxPauseRq_sync2;
957 255 mohor
    end
958
end
959
 
960
 
961
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
962
begin
963
  if(wb_rst_i)
964 352 olof
    TPauseRq <=  1'b0;
965 255 mohor
  else
966 352 olof
    TPauseRq <=  TxPauseRq_sync2 & (~TxPauseRq_sync3);
967 255 mohor
end
968
 
969
 
970 261 mohor
wire LatchedMRxErr;
971
reg RxAbort_latch;
972
reg RxAbort_sync1;
973
reg RxAbort_wb;
974
reg RxAbortRst_sync1;
975
reg RxAbortRst;
976 255 mohor
 
977 261 mohor
// Synchronizing RxAbort to the WISHBONE clock
978
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
979
begin
980
  if(wb_rst_i)
981 352 olof
    RxAbort_latch <=  1'b0;
982 365 olof
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr &
983
          ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
984 352 olof
    RxAbort_latch <=  1'b1;
985 261 mohor
  else if(RxAbortRst)
986 352 olof
    RxAbort_latch <=  1'b0;
987 261 mohor
end
988 255 mohor
 
989 261 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
990
begin
991
  if(wb_rst_i)
992
    begin
993 352 olof
      RxAbort_sync1 <=  1'b0;
994
      RxAbort_wb    <=  1'b0;
995
      RxAbort_wb    <=  1'b0;
996 261 mohor
    end
997
  else
998
    begin
999 352 olof
      RxAbort_sync1 <=  RxAbort_latch;
1000
      RxAbort_wb    <=  RxAbort_sync1;
1001 261 mohor
    end
1002
end
1003
 
1004
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
1005
begin
1006
  if(wb_rst_i)
1007
    begin
1008 352 olof
      RxAbortRst_sync1 <=  1'b0;
1009
      RxAbortRst       <=  1'b0;
1010 261 mohor
    end
1011
  else
1012
    begin
1013 352 olof
      RxAbortRst_sync1 <=  RxAbort_wb;
1014
      RxAbortRst       <=  RxAbortRst_sync1;
1015 261 mohor
    end
1016
end
1017
 
1018
 
1019
 
1020 114 mohor
// Connecting Wishbone module
1021 352 olof
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1022 349 olof
               .TX_FIFO_DEPTH     (TX_FIFO_DEPTH),
1023
               .TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH),
1024
               .RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH),
1025
               .RX_FIFO_DEPTH     (RX_FIFO_DEPTH),
1026
               .RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH))
1027
wishbone
1028 15 mohor
(
1029 365 olof
  .WB_CLK_I(wb_clk_i),
1030
  .WB_DAT_I(wb_dat_i),
1031
  .WB_DAT_O(BD_WB_DAT_O),
1032 15 mohor
 
1033
  // WISHBONE slave
1034 365 olof
  .WB_ADR_I(wb_adr_i[9:2]),
1035
  .WB_WE_I(wb_we_i),
1036
  .BDCs(BDCs),
1037
  .WB_ACK_O(BDAck),
1038
  .Reset(wb_rst_i),
1039 15 mohor
 
1040 41 mohor
  // WISHBONE master
1041 365 olof
  .m_wb_adr_o(m_wb_adr_tmp),
1042
  .m_wb_sel_o(m_wb_sel_o),
1043
  .m_wb_we_o(m_wb_we_o),
1044
  .m_wb_dat_i(m_wb_dat_i),
1045
  .m_wb_dat_o(m_wb_dat_o),
1046
  .m_wb_cyc_o(m_wb_cyc_o),
1047
  .m_wb_stb_o(m_wb_stb_o),
1048
  .m_wb_ack_i(m_wb_ack_i),
1049
  .m_wb_err_i(m_wb_err_i),
1050 214 mohor
 
1051
`ifdef ETH_WISHBONE_B3
1052 365 olof
  .m_wb_cti_o(m_wb_cti_o),
1053
  .m_wb_bte_o(m_wb_bte_o),
1054 214 mohor
`endif
1055 41 mohor
 
1056 15 mohor
    //TX
1057 365 olof
  .MTxClk(mtx_clk_pad_i),
1058
  .TxStartFrm(TxStartFrm),
1059
  .TxEndFrm(TxEndFrm),
1060
  .TxUsedData(TxUsedData),
1061
  .TxData(TxData),
1062
  .TxRetry(TxRetry),
1063
  .TxAbort(TxAbort),
1064
  .TxUnderRun(TxUnderRun),
1065
  .TxDone(TxDone),
1066
  .PerPacketCrcEn(PerPacketCrcEn),
1067
  .PerPacketPad(PerPacketPad),
1068 15 mohor
 
1069
  // Register
1070 365 olof
  .r_TxEn(r_TxEn),
1071
  .r_RxEn(r_RxEn),
1072
  .r_TxBDNum(r_TxBDNum),
1073
  .r_RxFlow(r_RxFlow),
1074
  .r_PassAll(r_PassAll),
1075 15 mohor
 
1076
  //RX
1077 365 olof
  .MRxClk(mrx_clk_pad_i),
1078
  .RxData(RxData),
1079
  .RxValid(RxValid),
1080
  .RxStartFrm(RxStartFrm),
1081
  .RxEndFrm(RxEndFrm),
1082
  .Busy_IRQ(Busy_IRQ),
1083
  .RxE_IRQ(RxE_IRQ),
1084
  .RxB_IRQ(RxB_IRQ),
1085
  .TxE_IRQ(TxE_IRQ),
1086
  .TxB_IRQ(TxB_IRQ),
1087 21 mohor
 
1088 365 olof
  .RxAbort(RxAbort_wb),
1089
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
1090 41 mohor
 
1091 365 olof
  .InvalidSymbol(InvalidSymbol),
1092
  .LatchedCrcError(LatchedCrcError),
1093
  .RxLength(RxByteCnt),
1094
  .RxLateCollision(RxLateCollision),
1095
  .ShortFrame(ShortFrame),
1096
  .DribbleNibble(DribbleNibble),
1097
  .ReceivedPacketTooBig(ReceivedPacketTooBig),
1098
  .LoadRxStatus(LoadRxStatus),
1099
  .RetryCntLatched(RetryCntLatched),
1100
  .RetryLimit(RetryLimit),
1101
  .LateCollLatched(LateCollLatched),
1102
  .DeferLatched(DeferLatched),
1103
  .RstDeferLatched(RstDeferLatched),
1104
  .CarrierSenseLost(CarrierSenseLost),
1105
  .ReceivedPacketGood(ReceivedPacketGood),
1106
  .AddressMiss(AddressMiss),
1107 261 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm)
1108 59 mohor
 
1109 210 mohor
`ifdef ETH_BIST
1110 218 mohor
  ,
1111 302 markom
  .mbist_si_i       (mbist_si_i),
1112
  .mbist_so_o       (mbist_so_o),
1113
  .mbist_ctrl_i       (mbist_ctrl_i)
1114 210 mohor
`endif
1115 360 olof
`ifdef WISHBONE_DEBUG
1116
  ,
1117
  .dbg_dat0(wb_dbg_dat0)
1118
`endif
1119
 
1120 15 mohor
);
1121
 
1122 327 igorm
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
1123 15 mohor
 
1124
// Connecting MacStatus module
1125 352 olof
eth_macstatus macstatus1
1126 15 mohor
(
1127 365 olof
  .MRxClk(mrx_clk_pad_i),
1128
  .Reset(wb_rst_i),
1129
  .ReceiveEnd(ReceiveEnd),
1130
  .ReceivedPacketGood(ReceivedPacketGood),
1131
     .ReceivedLengthOK(ReceivedLengthOK),
1132
  .RxCrcError(RxCrcError),
1133
  .MRxErr(MRxErr_Lb),
1134
  .MRxDV(MRxDV_Lb),
1135
  .RxStateSFD(RxStateSFD),
1136
  .RxStateData(RxStateData),
1137
  .RxStatePreamble(RxStatePreamble),
1138
  .RxStateIdle(RxStateIdle),
1139
  .Transmitting(Transmitting),
1140
  .RxByteCnt(RxByteCnt),
1141
  .RxByteCntEq0(RxByteCntEq0),
1142
  .RxByteCntGreat2(RxByteCntGreat2),
1143
  .RxByteCntMaxFrame(RxByteCntMaxFrame),
1144 261 mohor
  .InvalidSymbol(InvalidSymbol),
1145 365 olof
  .MRxD(MRxD_Lb),
1146
  .LatchedCrcError(LatchedCrcError),
1147
  .Collision(mcoll_pad_i),
1148
  .CollValid(r_CollValid),
1149
  .RxLateCollision(RxLateCollision),
1150
  .r_RecSmall(r_RecSmall),
1151
  .r_MinFL(r_MinFL),
1152
  .r_MaxFL(r_MaxFL),
1153
  .ShortFrame(ShortFrame),
1154
  .DribbleNibble(DribbleNibble),
1155
  .ReceivedPacketTooBig(ReceivedPacketTooBig),
1156
  .r_HugEn(r_HugEn),
1157
  .LoadRxStatus(LoadRxStatus),
1158
  .RetryCnt(RetryCnt),
1159
  .StartTxDone(StartTxDone),
1160
  .StartTxAbort(StartTxAbort),
1161
  .RetryCntLatched(RetryCntLatched),
1162
  .MTxClk(mtx_clk_pad_i),
1163
  .MaxCollisionOccured(MaxCollisionOccured),
1164
  .RetryLimit(RetryLimit),
1165
  .LateCollision(LateCollision),
1166
  .LateCollLatched(LateCollLatched),
1167
  .DeferIndication(DeferIndication),
1168
  .DeferLatched(DeferLatched),
1169
  .RstDeferLatched(RstDeferLatched),
1170
  .TxStartFrm(TxStartFrmOut),
1171
  .StatePreamble(StatePreamble),
1172
  .StateData(StateData),
1173
  .CarrierSense(CarrierSense_Tx2),
1174
  .CarrierSenseLost(CarrierSenseLost),
1175
  .TxUsedData(TxUsedDataIn),
1176
  .LatchedMRxErr(LatchedMRxErr),
1177
  .Loopback(r_LoopBck),
1178
  .r_FullD(r_FullD)
1179 15 mohor
);
1180
 
1181
 
1182
endmodule

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