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1 2 MichaelDun 
module Log2pipelined
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/*
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A fast base-2 logarithm function, 24 bits in, 8 bits out.
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Designed and coded by: Michael Dunn, http://www.cantares.on.ca/
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(more info at the web site - see "Extras")
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Executes every cycle, with a latency of 3.
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License: Free to use & modify, but please keep this header intact.
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July 18, 2010, Kitchener, Ontario, Canada
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This version not yet tested...
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*/
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(
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        input [23:0]     DIN,
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        input                   clk,
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        output  [7:0]    DOUT
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);
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// Comprises 3 main blocks: priority encoder, barrel shifter, and LUT
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reg     [3:0]    priencout1;
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reg     [3:0]    priencout2;
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reg     [3:0]    priencout3;
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reg     [4:0]    barrelout;
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reg     [20:0]   barrelin;
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reg     [3:0]    LUTout;
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always @(posedge clk)                                           // Basic top-level connectivity
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begin
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        priencout2      <=      priencout1;
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        priencout3      <=      priencout2;
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        barrelin        <=      DIN[23:3];
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end
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assign  DOUT    =       {priencout3, LUTout};
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wire [20:0] tmp1 =       (barrelin << ~priencout1);
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always @(posedge clk)                                           // Barrel shifter - OMG, it's a primitive in Verilog!
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begin
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        barrelout       <=      tmp1[19:15];
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end
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wire    [15:0]   priencin = DIN[23:8];
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always @(posedge clk)                                           // Priority encoder
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casex (priencin)
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        16'b1xxxxxxxxxxxxxxx:   priencout1      <=      15;
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        16'b01xxxxxxxxxxxxxx:   priencout1      <=      14;
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        16'b001xxxxxxxxxxxxx:   priencout1      <=      13;
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        16'b0001xxxxxxxxxxxx:   priencout1      <=      12;
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        16'b00001xxxxxxxxxxx:   priencout1      <=      11;
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        16'b000001xxxxxxxxxx:   priencout1      <=      10;
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        16'b0000001xxxxxxxxx:   priencout1      <=      9;
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        16'b00000001xxxxxxxx:   priencout1      <=      8;
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        16'b000000001xxxxxxx:   priencout1      <=      7;
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        16'b0000000001xxxxxx:   priencout1      <=      6;
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        16'b00000000001xxxxx:   priencout1      <=      5;
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        16'b000000000001xxxx:   priencout1      <=      4;
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        16'b0000000000001xxx:   priencout1      <=      3;
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        16'b00000000000001xx:   priencout1      <=      2;
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        16'b000000000000001x:   priencout1      <=      1;
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        16'b000000000000000x:   priencout1      <=      0;
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endcase
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/*
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LUT for log fraction lookup
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 - can be done with array or case:
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case (addr)
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0:out=0;
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.
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31:out=15;
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endcase
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        OR
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wire [3:0] lut [0:31];
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assign lut[0] = 0;
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.
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assign lut[31] = 15;
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Are there any better ways?
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*/
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// Let's try "case".
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// The equation is: output = log2(1+input/32)*16
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// For larger tables, better to generate a separate data file using a program!
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always @(posedge clk)
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case (barrelout)
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        0:       LUTout  <=      0;
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        1:      LUTout  <=      1;
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        2:      LUTout  <=      1;
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        3:      LUTout  <=      2;
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        4:      LUTout  <=      3;
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        5:      LUTout  <=      3;
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        6:      LUTout  <=      4;
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        7:      LUTout  <=      5;
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        8:      LUTout  <=      5;
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        9:      LUTout  <=      6;
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        10:     LUTout  <=      6;
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        11:     LUTout  <=      7;
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        12:     LUTout  <=      7;
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        13:     LUTout  <=      8;
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        14:     LUTout  <=      8;
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        15:     LUTout  <=      9;
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        16:     LUTout  <=      9;
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        17:     LUTout  <=      10;
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        18:     LUTout  <=      10;
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        19:     LUTout  <=      11;
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        20:     LUTout  <=      11;
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        21:     LUTout  <=      12;
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        22:     LUTout  <=      12;
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        23:     LUTout  <=      13;
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        24:     LUTout  <=      13;
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        25:     LUTout  <=      13;
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        26:     LUTout  <=      14;
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        27:     LUTout  <=      14;
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        28:     LUTout  <=      14;     // calculated value is *slightly* closer to 15, but 14 makes for a smoother curve!
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        29:     LUTout  <=      15;
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        30:     LUTout  <=      15;
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        31:     LUTout  <=      15;
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endcase
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endmodule

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