OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPMultiply.sv] - Blame information for rev 53

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 53 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      DFPMultiply.v
9
//              - decimal floating point multiplier
10
//              - can issue every clock cycle
11
//              - parameterized width
12
//
13
//
14
// BSD 3-Clause License
15
// Redistribution and use in source and binary forms, with or without
16
// modification, are permitted provided that the following conditions are met:
17
//
18
// 1. Redistributions of source code must retain the above copyright notice, this
19
//    list of conditions and the following disclaimer.
20
//
21
// 2. Redistributions in binary form must reproduce the above copyright notice,
22
//    this list of conditions and the following disclaimer in the documentation
23
//    and/or other materials provided with the distribution.
24
//
25
// 3. Neither the name of the copyright holder nor the names of its
26
//    contributors may be used to endorse or promote products derived from
27
//    this software without specific prior written permission.
28
//
29
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
//
40
//
41
//      Floating Point Multiplier
42
//
43
//      This multiplier handles denormalized numbers.
44
//      The output format is of an internal expanded representation
45
//      in preparation to be fed into a normalization unit, then
46
//      rounding. Basically, it's the same as the regular format
47
//      except the mantissa is doubled in size, the leading two
48
//      bits of which are assumed to be whole bits.
49
//
50
//
51
//      Floating Point Multiplier
52
//
53
//      Properties:
54
//      +-inf * +-inf = -+inf   (this is handled by exOver)
55
//      +-inf * 0     = QNaN
56
//
57
// ============================================================================
58
 
59
import fp::*;
60
 
61
module DFPMultiply(clk, ce, a, b, o, sign_exe, inf, overflow, underflow);
62
input clk;
63
input ce;
64
input  [127:0] a, b;
65
output [243:0] o;
66
output sign_exe;
67
output inf;
68
output overflow;
69
output underflow;
70
parameter DELAY =
71
  (FPWID == 128 ? 17 :
72
  FPWID == 80 ? 17 :
73
  FPWID == 64 ? 13 :
74
  FPWID == 40 ? 8 :
75
  FPWID == 32 ? 2 :
76
  FPWID == 16 ? 2 : 2);
77
 
78
reg [15:0] xo1;         // extra bit for sign
79
reg [215:0] mo1;
80
 
81
// constants
82
wire [15:0] infXp = 16'h9999;   // infinite / NaN - all ones
83
// The following is the value for an exponent of zero, with the offset
84
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
85
// The following is a template for a quiet nan. (MSB=1)
86
wire [107:0] qNaN  = {4'h1,{104{1'b0}}};
87
 
88
// variables
89
reg [215:0] sig1;
90
wire [15:0] ex2;
91
 
92
// Decompose the operands
93
wire sa, sb;                    // sign bit
94
wire [15:0] xa, xb;     // exponent bits
95
wire sxa, sxb;
96
wire [107:0] siga, sigb;
97
wire a_dn, b_dn;                        // a/b is denormalized
98
wire aNan, bNan, aNan1, bNan1;
99
wire az, bz;
100
wire aInf, bInf, aInf1, bInf1;
101
 
102
 
103
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
104
// Clock #1
105
// - decode the input operands
106
// - derive basic information
107
// - calculate exponent
108
// - calculate fraction
109
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
110
 
111
// -----------------------------------------------------------
112
// First clock
113
// -----------------------------------------------------------
114
 
115
reg under, over;
116
reg [15:0] sum_ex;
117
reg sx0;
118
 
119
DFPDecompose u1a (.i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
120
DFPDecompose u1b (.i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
121
 
122
// Compute the sum of the exponents.
123
// Exponents are sign-magnitude.
124
wire [15:0] xapxb, xamxb, xbmxa;
125
wire xapxbc, xamxbc, xbmxac;
126
BCDAddN #(.N(4)) u1c (.ci(1'b0), .a(xa), .b(xb), .o(xapxb), .co(xapxbc));
127
BCDSubN #(.N(4)) u1d (.ci(1'b0), .a(xa), .b(xb), .o(xamxb), .co(xamxbc));
128
BCDSubN #(.N(4)) u1e (.ci(1'b0), .a(xb), .b(xa), .o(xbmxa), .co(xbmxac));
129
 
130
always @*
131
        case({sxa,sxb})
132
        2'b11:  begin sum_ex <= xapxb; over <= xapxbc; under <= 1'b0; sx0 <= sxa; end
133
        2'b01:  begin sum_ex <= xbmxa; over <= 1'b0; under <= 1'b0; sx0 <= ~xbmxac; end
134
        2'b10:  begin sum_ex <= xamxb; over <= 1'b0; under <= 1'b0; sx0 <= ~xamxbc; end
135
        2'b00:  begin sum_ex <= xapxb; over <= 1'b0; under <= xapxbc; sx0 <= sxa; end
136
        endcase
137
 
138
wire [255:0] sigoo;
139
BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
140
 
141
always @(posedge clk)
142
  if (ce) sig1 <= sigoo[215:0];
143
 
144
// Status
145
wire under1, over1;
146
 
147
delay #(.WID(16),.DEP(DELAY)) u3 (.clk(clk), .ce(ce), .i(sum_ex), .o(ex2) );
148
delay #(.WID(1),.DEP(DELAY)) u2a (.clk(clk), .ce(ce), .i(aInf), .o(aInf1) );
149
delay #(.WID(1),.DEP(DELAY)) u2b (.clk(clk), .ce(ce), .i(bInf), .o(bInf1) );
150
delay #(.WID(1),.DEP(DELAY)) u6  (.clk(clk), .ce(ce), .i(under), .o(under1) );
151
delay #(.WID(1),.DEP(DELAY)) u7  (.clk(clk), .ce(ce), .i(over), .o(over1) );
152
 
153
// determine when a NaN is output
154
wire qNaNOut;
155
wire [127:0] a1,b1;
156
delay #(.WID(1),.DEP(DELAY)) u5 (.clk(clk), .ce(ce), .i((aInf&bz)|(bInf&az)), .o(qNaNOut) );
157
delay #(.WID(1),.DEP(DELAY)) u14 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
158
delay #(.WID(1),.DEP(DELAY)) u15 (.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
159
delay #(.WID(128),.DEP(DELAY))  u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );
160
delay #(.WID(128),.DEP(DELAY))  u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );
161
 
162
// -----------------------------------------------------------
163
// Second clock
164
// - correct xponent and mantissa for exceptional conditions
165
// -----------------------------------------------------------
166
 
167
wire so1, sx1;
168
reg [3:0] st;
169
 
170
delay #(.WID(1),.DEP(1)) u8 (.clk(clk), .ce(ce), .i(~(sa ^ sb)), .o(so1) );// two clock delay!
171
delay #(.WID(1),.DEP(1)) u9 (.clk(clk), .ce(ce), .i(sx0), .o(sx1) );// two clock delay!
172
 
173
always @(posedge clk)
174
        if (ce)
175
                casez({qNaNOut|aNan1|bNan1,aInf1,bInf1,over1,under1})
176
                5'b1????:       xo1 = infXp;    // qNaN - infinity * zero
177
                5'b01???:       xo1 = infXp;    // 'a' infinite
178
                5'b001??:       xo1 = infXp;    // 'b' infinite
179
                5'b0001?:       xo1 = infXp;    // result overflow
180
                5'b00001:       xo1 = ex2[15:0];//0;            // underflow
181
                default:        xo1 = ex2[15:0];        // situation normal
182
                endcase
183
 
184
// Force mantissa to zero when underflow or zero exponent when not supporting denormals.
185
always @(posedge clk)
186
        if (ce)
187
                casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1|under1})
188
                6'b1?????:  mo1 = {4'h1,a1[103:0],108'b0};
189
    6'b01????:  mo1 = {4'h1,b1[103:0],108'b0};
190
                6'b001???:      mo1 = {4'h1,qNaN|3'd4,108'b0};  // multiply inf * zero
191
                6'b0001??:      mo1 = 0;        // mul inf's
192
                6'b00001?:      mo1 = 0;        // mul inf's
193
                6'b000001:      mo1 = 0;        // mul overflow
194
                default:        mo1 = sig1;
195
                endcase
196
 
197
always @(posedge clk)
198
        if (ce) begin
199
                st[3] <= aNan1|bNan1;
200
                st[2] <= so1;
201
                st[1] <= aInf|bInf|over;
202
                st[0] <= sx1;
203
        end
204
 
205
delay #(.WID(1),.DEP(DELAY+1)) u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );
206
delay1 u11 (.clk(clk), .ce(ce), .i(over1),  .o(overflow) );
207
delay1 u12 (.clk(clk), .ce(ce), .i(over1),  .o(inf) );
208
delay1 u13 (.clk(clk), .ce(ce), .i(under1), .o(underflow) );
209
 
210
assign o = {st,xo1,mo1,8'h00};
211
 
212
endmodule
213
 
214
 
215
// Multiplier with normalization and rounding.
216
 
217
module DFPMultiplynr(clk, ce, a, b, o, rm, sign_exe, inf, overflow, underflow);
218
input clk;
219
input ce;
220
input  [127:0] a, b;
221
output [127:0] o;
222
input [2:0] rm;
223
output sign_exe;
224
output inf;
225
output overflow;
226
output underflow;
227
 
228
wire [243:0] o1;
229
wire sign_exe1, inf1, overflow1, underflow1;
230
wire [131:0] fpn0;
231
 
232
DFPMultiply  u1 (clk, ce, a, b, o1, sign_exe1, inf1, overflow1, underflow1);
233
DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
234
DFPRound     u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
235
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
236
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
237
delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
238
delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
239
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.