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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Blame information for rev 22

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1 15 rherveille
---------------------------------------------------------------------
2
----                                                             ----
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----  WISHBONE revB2 compl. I2C Master Core; bit-controller      ----
4
----                                                             ----
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----                                                             ----
6
----  Author: Richard Herveille                                  ----
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----          richard@asics.ws                                   ----
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----          www.asics.ws                                       ----
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----                                                             ----
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----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
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----                                                             ----
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---------------------------------------------------------------------
13
----                                                             ----
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---- Copyright (C) 2000 Richard Herveille                        ----
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----                    richard@asics.ws                         ----
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----                                                             ----
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---- This source file may be used and distributed without        ----
18
---- restriction provided that this copyright statement is not   ----
19
---- removed from the file and that any derivative work contains ----
20
---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
23
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
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---------------------------------------------------------------------
37
 
38
--  CVS Log
39
--
40 22 rherveille
--  $Id: i2c_master_bit_ctrl.vhd,v 1.2 2002-06-15 07:37:04 rherveille Exp $
41 15 rherveille
--
42 22 rherveille
--  $Date: 2002-06-15 07:37:04 $
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--  $Revision: 1.2 $
44 15 rherveille
--  $Author: rherveille $
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--  $Locker:  $
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--  $State: Exp $
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--
48
-- Change History:
49
--               $Log: not supported by cvs2svn $
50 22 rherveille
--               Revision 1.1  2001/11/05 12:02:33  rherveille
51
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
52
--               Code updated, is now up-to-date to doc. rev.0.4.
53
--               Added headers.
54
--
55 15 rherveille
 
56
 
57
--
58
-------------------------------------
59
-- Bit controller section
60
------------------------------------
61
--
62
-- Translate simple commands into SCL/SDA transitions
63
-- Each command has 5 states, A/B/C/D/idle
64
--
65
-- start:       SCL     ~~~~~~~~~~\____
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--      SDA     ~~~~~~~~\______
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--               x | A | B | C | D | i
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--
69
-- repstart     SCL     ____/~~~~\___
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--      SDA     __/~~~\______
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--               x | A | B | C | D | i
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--
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-- stop SCL     ____/~~~~~~~~
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--      SDA     ==\____/~~~~~
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--               x | A | B | C | D | i
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--
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--- write       SCL     ____/~~~~\____
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--      SDA     ==X=========X=
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--               x | A | B | C | D | i
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--
81
--- read        SCL     ____/~~~~\____
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--      SDA     XXXX=====XXXX
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--               x | A | B | C | D | i
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--
85
 
86
-- Timing:              Normal mode     Fast mode
87
-----------------------------------------------------------------
88
-- Fscl         100KHz          400KHz
89
-- Th_scl               4.0us           0.6us   High period of SCL
90
-- Tl_scl               4.7us           1.3us   Low period of SCL
91
-- Tsu:sta              4.7us           0.6us   setup time for a repeated start condition
92
-- Tsu:sto              4.0us           0.6us   setup time for a stop conditon
93
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
94
--
95
 
96
library ieee;
97
use ieee.std_logic_1164.all;
98
use ieee.std_logic_arith.all;
99
 
100
entity i2c_master_bit_ctrl is
101
        generic(
102
                Tcq : time := 1 ns
103
        );
104
        port (
105
                clk    : in std_logic;
106
                rst    : in std_logic;
107
                nReset : in std_logic;
108
                ena    : in std_logic;                          -- core enable signal
109
 
110
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
111
 
112
                cmd     : in std_logic_vector(3 downto 0);
113
                cmd_ack : out std_logic;
114
                busy    : out std_logic;
115
 
116
                din  : in std_logic;
117
                dout : out std_logic;
118
 
119
                -- i2c lines
120
                scl_i   : in std_logic;  -- i2c clock line input
121
                scl_o   : out std_logic; -- i2c clock line output
122
                scl_oen : out std_logic; -- i2c clock line output enable, active low
123
                sda_i   : in std_logic;  -- i2c data line input
124
                sda_o   : out std_logic; -- i2c data line output
125
                sda_oen : out std_logic  -- i2c data line output enable, active low
126
        );
127
end entity i2c_master_bit_ctrl;
128
 
129
architecture structural of i2c_master_bit_ctrl is
130 22 rherveille
        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
131
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
132
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
133
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
134
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
135 15 rherveille
 
136
        type states is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
137
        signal c_state : states;
138
 
139 22 rherveille
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
140
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
141
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
142 15 rherveille
 
143 22 rherveille
        signal clk_en, slave_wait :std_logic;           -- clock generation signals
144
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
145 15 rherveille
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
146
 
147
begin
148
        -- synchronize SCL and SDA inputs
149
        synch_scl_sda: process(clk)
150
        begin
151
                if (clk'event and clk = '1') then
152
                        sSCL <= scl_i after Tcq;
153
                        sSDA <= sda_i after Tcq;
154
                end if;
155
        end process synch_SCL_SDA;
156
 
157 22 rherveille
        -- delay scl_oen
158
        process (clk)
159
        begin
160
                if (clk'event and clk = '1') then
161
                        dscl_oen <= iscl_oen after Tcq;
162
                end if;
163
        end process;
164
 
165 15 rherveille
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
166 22 rherveille
        slave_wait <= dscl_oen and not sSCL;
167 15 rherveille
 
168
        -- generate clk enable signal
169
        gen_clken: process(clk, nReset)
170
        begin
171
                if (nReset = '0') then
172
                        cnt    <= (others => '0') after Tcq;
173
                        clk_en <= '1' after Tcq;
174
                elsif (clk'event and clk = '1') then
175
                        if (rst = '1') then
176
                                cnt    <= (others => '0') after Tcq;
177
                                clk_en <= '1' after Tcq;
178
                        else
179
                                if ( (cnt = 0) or (ena = '0') ) then
180
                                        clk_en <= '1' after Tcq;
181
                                        cnt    <= clk_cnt after Tcq;
182
                                else
183
                                        if (slave_wait = '0') then
184
                                                cnt <= cnt -1 after Tcq;
185
                                        end if;
186
                                        clk_en <= '0' after Tcq;
187
                                end if;
188
                        end if;
189
                end if;
190
        end process gen_clken;
191
 
192
 
193
        -- generate bus status controller
194
        bus_status_ctrl: block
195
                signal dSDA : std_logic;
196
                signal sta_condition : std_logic;
197
                signal sto_condition : std_logic;
198
 
199
                signal ibusy : std_logic;
200
        begin
201
                -- detect start condition => detect falling edge on SDA while SCL is high
202
                -- detect stop condition  => detect rising edge on SDA while SCL is high
203
                detect_sta_sto: process(clk)
204
                begin
205
                        if (clk'event and clk = '1') then
206
                                dSDA <= sSDA;   -- generate a delayed version of sSDA
207
 
208
                                sta_condition <= (not sSDA and dSDA) and sSCL;
209
                                sto_condition <= (sSDA and not dSDA) and sSCL;
210
                        end if;
211
                end process detect_sta_sto;
212
 
213
                -- generate bus busy signal
214
                gen_busy: process(clk, nReset)
215
                begin
216
                        if (nReset = '0') then
217
                                ibusy <= '0' after Tcq;
218
                        elsif (clk'event and clk = '1') then
219
                                if (rst = '1') then
220
                                        ibusy <= '0' after Tcq;
221
                                else
222
                                        ibusy <= (sta_condition or ibusy) and not sto_condition after Tcq;
223
                                end if;
224
                        end if;
225
                end process gen_busy;
226
 
227
                -- assign output
228
                busy <= ibusy;
229
        end block bus_status_ctrl;
230
 
231
 
232
        -- generate statemachine
233
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
234
                variable nxt_state : states;
235
                variable icmd_ack, store_sda : std_logic;
236
        begin
237
 
238
                nxt_state := c_state;
239
 
240
                icmd_ack := '0'; -- default no acknowledge
241
 
242
                store_sda := '0';
243
 
244
                case (c_state) is
245
                        -- idle
246
                        when idle =>
247
                                case cmd is
248
                                        when I2C_CMD_START =>
249
                                                nxt_state := start_a;
250
 
251
                                        when I2C_CMD_STOP =>
252
                                                nxt_state := stop_a;
253
 
254
                                        when I2C_CMD_WRITE =>
255
                                                nxt_state := wr_a;
256
 
257
                                        when I2C_CMD_READ =>
258
                                                nxt_state := rd_a;
259
 
260
                                        when others =>  -- NOP command
261
                                                nxt_state := idle;
262
                                end case;
263
 
264
                        -- start
265
                        when start_a =>
266
                                nxt_state := start_b;
267
 
268
                        when start_b =>
269
                                nxt_state := start_c;
270
 
271
                        when start_c =>
272
                                nxt_state := start_d;
273
 
274
                        when start_d =>
275
                                nxt_state := idle;
276
                                icmd_ack := '1'; -- command completed
277
 
278
                        -- stop
279
                        when stop_a =>
280
                                nxt_state := stop_b;
281
 
282
                        when stop_b =>
283
                                nxt_state := stop_c;
284
 
285
                        when stop_c =>
286
                                nxt_state := idle;
287
                                icmd_ack := '1'; -- command completed
288
 
289
                        -- read
290
                        when rd_a =>
291
                                nxt_state := rd_b;
292
 
293
                        when rd_b =>
294
                                nxt_state := rd_c;
295
 
296
                        when rd_c =>
297
                                nxt_state := rd_d;
298
                                store_sda := '1';
299
 
300
                        when rd_d =>
301
                                nxt_state := idle;
302
                                icmd_ack := '1'; -- command completed
303
 
304
                        -- write
305
                        when wr_a =>
306
                                nxt_state := wr_b;
307
 
308
                        when wr_b =>
309
                                nxt_state := wr_c;
310
 
311
                        when wr_c =>
312
                                nxt_state := wr_d;
313
 
314
                        when wr_d =>
315
                                nxt_state := idle;
316
                                icmd_ack := '1'; -- command completed
317
 
318
                end case;
319
 
320
                -- generate regs
321
                if (nReset = '0') then
322
                        c_state <= idle after Tcq;
323
                        cmd_ack <= '0' after Tcq;
324
                        Dout    <= '0' after Tcq;
325
                elsif (clk'event and clk = '1') then
326
                        if (rst = '1') then
327
                                c_state <= idle after Tcq;
328
                                cmd_ack <= '0' after Tcq;
329
                                Dout    <= '0' after Tcq;
330
                        else
331
                                if (clk_en = '1') then
332
                                        c_state <= nxt_state after Tcq;
333
 
334
                                        if (store_sda = '1') then
335
                                                dout <= sSDA after Tcq;
336
                                        end if;
337
                                end if;
338
 
339
                                cmd_ack <= icmd_ack and clk_en;
340
                        end if;
341
                end if;
342
        end process nxt_state_decoder;
343
 
344
        --
345
        -- convert states to SCL and SDA signals
346
        --
347
        output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
348
                variable iscl, isda : std_logic;
349
        begin
350
                case (c_state) is
351
                        when idle =>
352
                                iscl := iscl_oen; -- keep SCL in same state
353
                                isda := isda_oen; -- keep SDA in same state
354
 
355
                        -- start
356
                        when start_a =>
357
                                iscl := iscl_oen; -- keep SCL in same state (for repeated start)
358
                                isda := '1';      -- set SDA high
359
 
360
                        when start_b =>
361
                                iscl := '1';    -- set SCL high
362
                                isda := '1'; -- keep SDA high
363
 
364
                        when start_c =>
365
                                iscl := '1';    -- keep SCL high
366
                                isda := '0'; -- sel SDA low
367
 
368
                        when start_d =>
369
                                iscl := '0'; -- set SCL low
370
                                isda := '0'; -- keep SDA low
371
 
372
                        -- stop
373
                        when stop_a =>
374
                                iscl := '0'; -- keep SCL disabled
375
                                isda := '0'; -- set SDA low
376
 
377
                        when stop_b =>
378
                                iscl := '1'; -- set SCL high
379
                                isda := '0'; -- keep SDA low
380
 
381
                        when stop_c =>
382
                                iscl := '1'; -- keep SCL high
383
                                isda := '1'; -- set SDA high
384
 
385
                        -- write
386
                        when wr_a =>
387
                                iscl := '0';     -- keep SCL low
388
                                isda := din; -- set SDA
389
 
390
                        when wr_b =>
391
                                iscl := '1';    -- set SCL high
392
                                isda := din; -- keep SDA
393
 
394
                        when wr_c =>
395
                                iscl := '1';    -- keep SCL high
396
                                isda := din; -- keep SDA
397
 
398
                        when wr_d =>
399
                                iscl := '0'; -- set SCL low
400
                                isda := din; -- keep SDA
401
 
402
                        -- read
403
                        when rd_a =>
404
                                iscl := '0'; -- keep SCL low
405
                                isda := '1'; -- tri-state SDA
406
 
407
                        when rd_b =>
408
                                iscl := '1'; -- set SCL high
409
                                isda := '1'; -- tri-state SDA
410
 
411
                        when rd_c =>
412
                                iscl := '1'; -- keep SCL high
413
                                isda := '1'; -- tri-state SDA
414
 
415
                        when rd_d =>
416
                                iscl := '0'; -- set SCL low
417
                                isda := '1'; -- tri-state SDA
418
                end case;
419
 
420
                -- generate registers
421
                if (nReset = '0') then
422
                        iscl_oen <= '1' after Tcq;
423
                        isda_oen <= '1' after Tcq;
424
                elsif (clk'event and clk = '1') then
425
                        if (rst = '1') then
426
                                iscl_oen <= '1' after Tcq;
427
                                isda_oen <= '1' after Tcq;
428
                        else
429
                                if (clk_en = '1') then
430
                                        iscl_oen <= iscl after Tcq;
431
                                        isda_oen <= isda after Tcq;
432
                                end if;
433
                        end if;
434
                end if;
435
        end process output_decoder;
436
 
437
        -- assign outputs
438
        scl_o   <= '0';
439
        scl_oen <= iscl_oen;
440
        sda_o   <= '0';
441
        sda_oen <= isda_oen;
442
end architecture structural;

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