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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Blame information for rev 27

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---------------------------------------------------------------------
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----                                                             ----
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----  WISHBONE revB2 I2C Master Core; bit-controller             ----
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----                                                             ----
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----                                                             ----
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----  Author: Richard Herveille                                  ----
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----          richard@asics.ws                                   ----
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----          www.asics.ws                                       ----
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----                                                             ----
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----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
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----                                                             ----
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---------------------------------------------------------------------
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----                                                             ----
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---- Copyright (C) 2000 Richard Herveille                        ----
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----                    richard@asics.ws                         ----
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----                                                             ----
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---- This source file may be used and distributed without        ----
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---- restriction provided that this copyright statement is not   ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
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---------------------------------------------------------------------
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38
--  CVS Log
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--
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--  $Id: i2c_master_bit_ctrl.vhd,v 1.4 2002-11-30 22:24:37 rherveille Exp $
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--
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--  $Date: 2002-11-30 22:24:37 $
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--  $Revision: 1.4 $
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--  $Author: rherveille $
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--  $Locker:  $
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--  $State: Exp $
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--
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-- Change History:
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--               $Log: not supported by cvs2svn $
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--               Revision 1.3  2002/10/30 18:09:53  rherveille
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--               Fixed some reported minor start/stop generation timing issuess.
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--
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--               Revision 1.2  2002/06/15 07:37:04  rherveille
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--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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--
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--               Revision 1.1  2001/11/05 12:02:33  rherveille
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--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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--               Code updated, is now up-to-date to doc. rev.0.4.
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--               Added headers.
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--
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--
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-------------------------------------
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-- Bit controller section
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------------------------------------
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--
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-- Translate simple commands into SCL/SDA transitions
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-- Each command has 5 states, A/B/C/D/idle
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--
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-- start:       SCL     ~~~~~~~~~~\____
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--      SDA     ~~~~~~~~\______
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--               x | A | B | C | D | i
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--
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-- repstart     SCL     ____/~~~~\___
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--      SDA     __/~~~\______
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--               x | A | B | C | D | i
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--
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-- stop SCL     ____/~~~~~~~~
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--      SDA     ==\____/~~~~~
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--               x | A | B | C | D | i
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--
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--- write       SCL     ____/~~~~\____
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--      SDA     ==X=========X=
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--               x | A | B | C | D | i
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--
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--- read        SCL     ____/~~~~\____
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--      SDA     XXXX=====XXXX
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--               x | A | B | C | D | i
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--
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-- Timing:      Normal mode     Fast mode
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-----------------------------------------------------------------
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-- Fscl         100KHz          400KHz
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-- Th_scl       4.0us           0.6us   High period of SCL
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-- Tl_scl       4.7us           1.3us   Low period of SCL
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-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
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-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
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-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
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--
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102
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity i2c_master_bit_ctrl is
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        port (
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                clk    : in std_logic;
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                rst    : in std_logic;
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                nReset : in std_logic;
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                ena    : in std_logic;                          -- core enable signal
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                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
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                cmd     : in std_logic_vector(3 downto 0);
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                cmd_ack : out std_logic;
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                busy    : out std_logic;
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                din  : in std_logic;
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                dout : out std_logic;
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                -- i2c lines
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                scl_i   : in std_logic;  -- i2c clock line input
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                scl_o   : out std_logic; -- i2c clock line output
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                scl_oen : out std_logic; -- i2c clock line output enable, active low
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                sda_i   : in std_logic;  -- i2c data line input
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                sda_o   : out std_logic; -- i2c data line output
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                sda_oen : out std_logic  -- i2c data line output enable, active low
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        );
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end entity i2c_master_bit_ctrl;
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architecture structural of i2c_master_bit_ctrl is
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        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
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        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
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        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
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        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
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        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
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        type states is (idle, start_a, start_b, start_c, start_d, start_e,
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                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
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        signal c_state : states;
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        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
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        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
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        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
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        signal clk_en, slave_wait :std_logic;           -- clock generation signals
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--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
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        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
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151
begin
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        -- synchronize SCL and SDA inputs
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        synch_scl_sda: process(clk)
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        begin
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            if (clk'event and clk = '1') then
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              sSCL <= scl_i;
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              sSDA <= sda_i;
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            end if;
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        end process synch_SCL_SDA;
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        -- delay scl_oen
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        process (clk)
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        begin
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            if (clk'event and clk = '1') then
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              dscl_oen <= iscl_oen;
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            end if;
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        end process;
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        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
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        slave_wait <= dscl_oen and not sSCL;
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172
        -- generate clk enable signal
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        gen_clken: process(clk, nReset)
174
        begin
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            if (nReset = '0') then
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              cnt    <= (others => '0');
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              clk_en <= '1';
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            elsif (clk'event and clk = '1') then
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              if (rst = '1') then
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                cnt    <= (others => '0');
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                clk_en <= '1';
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              else
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                if ( (cnt = 0) or (ena = '0') ) then
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                  clk_en <= '1';
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                  cnt    <= clk_cnt;
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                else
187
                  if (slave_wait = '0') then
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                    cnt <= cnt -1;
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                  end if;
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                  clk_en <= '0';
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                end if;
192
              end if;
193
            end if;
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        end process gen_clken;
195
 
196
 
197
        -- generate bus status controller
198
        bus_status_ctrl: block
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          signal dSDA : std_logic;
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          signal sta_condition : std_logic;
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          signal sto_condition : std_logic;
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          signal ibusy : std_logic;
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        begin
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            -- detect start condition => detect falling edge on SDA while SCL is high
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            -- detect stop condition  => detect rising edge on SDA while SCL is high
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            detect_sta_sto: process(clk)
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            begin
209
                if (clk'event and clk = '1') then
210
                  dSDA <= sSDA; -- generate a delayed version of sSDA
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                  sta_condition <= (not sSDA and dSDA) and sSCL;
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                  sto_condition <= (sSDA and not dSDA) and sSCL;
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                end if;
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            end process detect_sta_sto;
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            -- generate bus busy signal
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            gen_busy: process(clk, nReset)
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            begin
220
                if (nReset = '0') then
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                  ibusy <= '0';
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                elsif (clk'event and clk = '1') then
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                  if (rst = '1') then
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                    ibusy <= '0';
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                  else
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                    ibusy <= (sta_condition or ibusy) and not sto_condition;
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                  end if;
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                end if;
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            end process gen_busy;
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            -- assign output
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            busy <= ibusy;
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        end block bus_status_ctrl;
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        -- generate statemachine
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        nxt_state_decoder : process (clk, nReset, c_state, cmd)
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        begin
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            if (nReset = '0') then
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              c_state  <= idle;
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              cmd_ack  <= '0';
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              dout     <= '0';
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              iscl_oen <= '1';
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              isda_oen <= '1';
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            elsif (clk'event and clk = '1') then
246
              if (rst = '1') then
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                c_state  <= idle;
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                cmd_ack  <= '0';
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                dout     <= '0';
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                iscl_oen <= '1';
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                isda_oen <= '1';
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              else
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                cmd_ack <= '0'; -- default no acknowledge
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                if (clk_en = '1') then
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                  case (c_state) is
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                     -- idle
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                     when idle =>
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                        case cmd is
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                          when I2C_CMD_START => c_state <= start_a;
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                          when I2C_CMD_STOP  => c_state <= stop_a;
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                          when I2C_CMD_WRITE => c_state <= wr_a;
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                          when I2C_CMD_READ  => c_state <= rd_a;
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                          when others        => c_state <= idle; -- NOP command
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                        end case;
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                        iscl_oen <= iscl_oen; -- keep SCL in same state
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                        isda_oen <= isda_oen; -- keep SDA in same state
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                     -- start
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                     when start_a =>
272
                        c_state  <= start_b;
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                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
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                        isda_oen <= '1';      -- set SDA high
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                     when start_b =>
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                        c_state  <= start_c;
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                        iscl_oen <= '1'; -- set SCL high
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                        isda_oen <= '1'; -- keep SDA high
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                     when start_c =>
282
                        c_state  <= start_d;
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                        iscl_oen <= '1'; -- keep SCL high
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                        isda_oen <= '0'; -- set SDA low
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                     when start_d =>
287
                        c_state  <= start_e;
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                        iscl_oen <= '1'; -- keep SCL high
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                        isda_oen <= '0'; -- keep SDA low
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                     when start_e =>
292
                        c_state  <= idle;
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                        cmd_ack  <= '1'; -- command completed
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                        iscl_oen <= '0'; -- set SCL low
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                        isda_oen <= '0'; -- keep SDA low
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                     -- stop
298
                     when stop_a =>
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                        c_state  <= stop_b;
300
                        iscl_oen <= '0'; -- keep SCL disabled
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                        isda_oen <= '0'; -- set SDA low
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                     when stop_b =>
304
                        c_state  <= stop_c;
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                        iscl_oen <= '1'; -- set SCL high
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                        isda_oen <= '0'; -- keep SDA low
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                     when stop_c =>
309
                        c_state  <= stop_d;
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                        iscl_oen <= '1'; -- keep SCL high
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                        isda_oen <= '0'; -- keep SDA low
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                     when stop_d =>
314
                        c_state  <= idle;
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                        cmd_ack  <= '1'; -- command completed
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                        iscl_oen <= '1'; -- keep SCL high
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                        isda_oen <= '1'; -- set SDA high
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                     -- read
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                     when rd_a =>
321
                        c_state  <= rd_b;
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                        iscl_oen <= '0'; -- keep SCL low
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                        isda_oen <= '1'; -- tri-state SDA
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                     when rd_b =>
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                        c_state  <= rd_c;
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                        iscl_oen <= '1'; -- set SCL high
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                        isda_oen <= '1'; -- tri-state SDA
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                     when rd_c =>
331
                        c_state  <= rd_d;
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                        dout     <= sSDA;
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                        iscl_oen <= '1'; -- keep SCL high
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                        isda_oen <= '1'; -- tri-state SDA
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                     when rd_d =>
337
                        c_state  <= idle;
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                        cmd_ack  <= '1'; -- command completed
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                        iscl_oen <= '0'; -- set SCL low
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                        isda_oen <= '1'; -- tri-state SDA
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                     -- write
343
                     when wr_a =>
344
                        c_state  <= wr_b;
345
                        iscl_oen <= '0'; -- keep SCL low
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                        isda_oen <= din; -- set SDA
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                     when wr_b =>
349
                        c_state  <= wr_c;
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                        iscl_oen <= '1'; -- set SCL high
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                        isda_oen <= din; -- keep SDA
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                     when wr_c =>
354
                        c_state  <= wr_d;
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                        iscl_oen <= '1'; -- keep SCL high
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                        isda_oen <= din; -- keep SDA
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                     when wr_d =>
359
                        c_state  <= idle;
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                        cmd_ack  <= '1'; -- command completed
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                        iscl_oen <= '0'; -- set SCL low
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                        isda_oen <= din; -- keep SDA
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                     when others =>
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366 27 rherveille
                  end case;
367 24 rherveille
                end if;
368
              end if;
369
            end if;
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        end process nxt_state_decoder;
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372
 
373
        -- assign outputs
374
        scl_o   <= '0';
375
        scl_oen <= iscl_oen;
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        sda_o   <= '0';
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        sda_oen <= isda_oen;
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end architecture structural;

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