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---------------------------------------------------------------------
2
----                                                             ----
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----  WISHBONE revB2 I2C Master Core; bit-controller             ----
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----                                                             ----
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----                                                             ----
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----  Author: Richard Herveille                                  ----
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----          richard@asics.ws                                   ----
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----          www.asics.ws                                       ----
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----                                                             ----
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----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
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----                                                             ----
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---------------------------------------------------------------------
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----                                                             ----
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---- Copyright (C) 2000 Richard Herveille                        ----
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----                    richard@asics.ws                         ----
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----                                                             ----
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---- This source file may be used and distributed without        ----
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---- restriction provided that this copyright statement is not   ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
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---------------------------------------------------------------------
37
 
38
--  CVS Log
39
--
40 34 rherveille
--  $Id: i2c_master_bit_ctrl.vhd,v 1.6 2003-02-01 02:03:06 rherveille Exp $
41 15 rherveille
--
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--  $Date: 2003-02-01 02:03:06 $
43
--  $Revision: 1.6 $
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--  $Author: rherveille $
45
--  $Locker:  $
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--  $State: Exp $
47
--
48
-- Change History:
49
--               $Log: not supported by cvs2svn $
50 34 rherveille
--               Revision 1.5  2002/12/26 16:05:47  rherveille
51
--               Core is now a Multimaster I2C controller.
52
--
53 31 rherveille
--               Revision 1.4  2002/11/30 22:24:37  rherveille
54
--               Cleaned up code
55
--
56 27 rherveille
--               Revision 1.3  2002/10/30 18:09:53  rherveille
57
--               Fixed some reported minor start/stop generation timing issuess.
58
--
59 24 rherveille
--               Revision 1.2  2002/06/15 07:37:04  rherveille
60
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
61
--
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--               Revision 1.1  2001/11/05 12:02:33  rherveille
63
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
64
--               Code updated, is now up-to-date to doc. rev.0.4.
65
--               Added headers.
66
--
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68
 
69
--
70
-------------------------------------
71
-- Bit controller section
72
------------------------------------
73
--
74
-- Translate simple commands into SCL/SDA transitions
75
-- Each command has 5 states, A/B/C/D/idle
76
--
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-- start:    SCL  ~~~~~~~~~~~~~~\____
78
--           SDA  XX/~~~~~~~\______
79
--                x | A | B | C | D | i
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--
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-- repstart  SCL  ______/~~~~~~~\___
82
--           SDA  __/~~~~~~~\______
83
--                x | A | B | C | D | i
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--
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-- stop      SCL  _______/~~~~~~~~~~~
86
--           SDA  ==\___________/~~~~~
87
--                x | A | B | C | D | i
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--
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--- write    SCL  ______/~~~~~~~\____
90
--           SDA  XXX===============XX
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--                x | A | B | C | D | i
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--
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--- read     SCL  ______/~~~~~~~\____
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--           SDA  XXXXXXX=XXXXXXXXXXX
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--                x | A | B | C | D | i
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--
97
 
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-- Timing:      Normal mode     Fast mode
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-----------------------------------------------------------------
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-- Fscl         100KHz          400KHz
101
-- Th_scl       4.0us           0.6us   High period of SCL
102
-- Tl_scl       4.7us           1.3us   Low period of SCL
103
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
104
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
105
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
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--
107
 
108
library ieee;
109
use ieee.std_logic_1164.all;
110
use ieee.std_logic_arith.all;
111
 
112
entity i2c_master_bit_ctrl is
113
        port (
114
                clk    : in std_logic;
115
                rst    : in std_logic;
116
                nReset : in std_logic;
117
                ena    : in std_logic;                          -- core enable signal
118
 
119
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
120
 
121
                cmd     : in std_logic_vector(3 downto 0);
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                cmd_ack : out std_logic; -- command completed
123
                busy    : out std_logic; -- i2c bus busy
124
                al      : out std_logic; -- arbitration lost
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126
                din  : in std_logic;
127
                dout : out std_logic;
128
 
129
                -- i2c lines
130
                scl_i   : in std_logic;  -- i2c clock line input
131
                scl_o   : out std_logic; -- i2c clock line output
132
                scl_oen : out std_logic; -- i2c clock line output enable, active low
133
                sda_i   : in std_logic;  -- i2c data line input
134
                sda_o   : out std_logic; -- i2c data line output
135
                sda_oen : out std_logic  -- i2c data line output enable, active low
136
        );
137
end entity i2c_master_bit_ctrl;
138
 
139
architecture structural of i2c_master_bit_ctrl is
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        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
141
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
142
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
143
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
144
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
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146 27 rherveille
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
147 24 rherveille
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
148 15 rherveille
        signal c_state : states;
149
 
150 22 rherveille
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
151 31 rherveille
        signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
152
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
153 22 rherveille
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
154 34 rherveille
        signal clk_en, slave_wait : std_logic;          -- clock generation signals
155
        signal ial                : std_logic;          -- internal arbitration lost signal
156 22 rherveille
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
157 15 rherveille
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
158
 
159
begin
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        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
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        -- delay scl_oen
162
        process (clk)
163
        begin
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            if (clk'event and clk = '1') then
165 27 rherveille
              dscl_oen <= iscl_oen;
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            end if;
167 22 rherveille
        end process;
168
        slave_wait <= dscl_oen and not sSCL;
169 15 rherveille
 
170
        -- generate clk enable signal
171
        gen_clken: process(clk, nReset)
172
        begin
173 24 rherveille
            if (nReset = '0') then
174 27 rherveille
              cnt    <= (others => '0');
175
              clk_en <= '1';
176 24 rherveille
            elsif (clk'event and clk = '1') then
177
              if (rst = '1') then
178 27 rherveille
                cnt    <= (others => '0');
179
                clk_en <= '1';
180 24 rherveille
              else
181
                if ( (cnt = 0) or (ena = '0') ) then
182 31 rherveille
                  if (slave_wait = '0') then
183
                    cnt    <= clk_cnt;
184
                    clk_en <= '1';
185
                  else
186
                    cnt    <= cnt;
187
                    clk_en <= '0';
188
                  end if;
189 24 rherveille
                else
190
                  if (slave_wait = '0') then
191 27 rherveille
                    cnt <= cnt -1;
192 24 rherveille
                  end if;
193 27 rherveille
                  clk_en <= '0';
194 24 rherveille
                end if;
195
              end if;
196
            end if;
197 15 rherveille
        end process gen_clken;
198
 
199
 
200
        -- generate bus status controller
201
        bus_status_ctrl: block
202 31 rherveille
          signal dSCL, dSDA          : std_logic;  -- delayes sSCL and sSDA
203
          signal sta_condition       : std_logic;  -- start detected
204
          signal sto_condition       : std_logic;  -- stop detected
205
          signal cmd_stop, dcmd_stop : std_logic;  -- STOP command
206
          signal ibusy               : std_logic;  -- internal busy signal
207
        begin
208
            -- synchronize SCL and SDA inputs
209
            synch_scl_sda: process(clk)
210
            begin
211
                if (clk'event and clk = '1') then
212
                  sSCL <= scl_i;
213
                  sSDA <= sda_i;
214 15 rherveille
 
215 31 rherveille
                  dSCL <= sSCL;
216
                  dSDA <= sSDA;
217
                end if;
218
            end process synch_SCL_SDA;
219
 
220 24 rherveille
            -- detect start condition => detect falling edge on SDA while SCL is high
221
            -- detect stop condition  => detect rising edge on SDA while SCL is high
222
            detect_sta_sto: process(clk)
223
            begin
224
                if (clk'event and clk = '1') then
225
                  sta_condition <= (not sSDA and dSDA) and sSCL;
226
                  sto_condition <= (sSDA and not dSDA) and sSCL;
227
                end if;
228
            end process detect_sta_sto;
229 15 rherveille
 
230 31 rherveille
            -- generate i2c-bus busy signal
231 24 rherveille
            gen_busy: process(clk, nReset)
232
            begin
233
                if (nReset = '0') then
234 27 rherveille
                  ibusy <= '0';
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                elsif (clk'event and clk = '1') then
236
                  if (rst = '1') then
237 27 rherveille
                    ibusy <= '0';
238 24 rherveille
                  else
239 27 rherveille
                    ibusy <= (sta_condition or ibusy) and not sto_condition;
240 24 rherveille
                  end if;
241
                end if;
242
            end process gen_busy;
243 31 rherveille
            busy <= ibusy;
244 15 rherveille
 
245 31 rherveille
 
246
            -- generate arbitration lost signal
247
            gen_al: process(clk)
248
            begin
249
              if (clk'event and clk = '1') then
250
                    if (cmd = I2C_CMD_STOP) then
251
                  cmd_stop <= '1';
252
                        else
253
                          cmd_stop <= '0';
254
                        end if;
255
                dcmd_stop <= cmd_stop;
256
 
257
                al <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop);
258
              end if;
259
            end process gen_al;
260 34 rherveille
            ial <= al;
261
 
262 31 rherveille
            -- generate dout signal, store dout on rising edge of SCL
263
            gen_dout: process(clk)
264
            begin
265
              if (clk'event and clk = '1') then
266
                if (sSCL = '1' and dSCL = '0') then
267
                  dout <= sSDA;
268
                end if;
269
              end if;
270
            end process gen_dout;
271 15 rherveille
        end block bus_status_ctrl;
272
 
273
 
274
        -- generate statemachine
275
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
276
        begin
277 27 rherveille
            if (nReset = '0') then
278
              c_state  <= idle;
279
              cmd_ack  <= '0';
280
              iscl_oen <= '1';
281
              isda_oen <= '1';
282 31 rherveille
              sda_chk  <= '0';
283 27 rherveille
            elsif (clk'event and clk = '1') then
284 34 rherveille
              if (rst = '1' or ial = '1') then
285 27 rherveille
                c_state  <= idle;
286
                cmd_ack  <= '0';
287
                iscl_oen <= '1';
288
                isda_oen <= '1';
289 31 rherveille
                sda_chk  <= '0';
290 27 rherveille
              else
291
                cmd_ack <= '0'; -- default no acknowledge
292 15 rherveille
 
293 27 rherveille
                if (clk_en = '1') then
294
                  case (c_state) is
295
                     -- idle
296
                     when idle =>
297
                        case cmd is
298
                          when I2C_CMD_START => c_state <= start_a;
299
                          when I2C_CMD_STOP  => c_state <= stop_a;
300
                          when I2C_CMD_WRITE => c_state <= wr_a;
301
                          when I2C_CMD_READ  => c_state <= rd_a;
302
                          when others        => c_state <= idle; -- NOP command
303
                        end case;
304 15 rherveille
 
305 27 rherveille
                        iscl_oen <= iscl_oen; -- keep SCL in same state
306
                        isda_oen <= isda_oen; -- keep SDA in same state
307 31 rherveille
                        sda_chk  <= '0';      -- don't check SDA
308 15 rherveille
 
309 27 rherveille
                     -- start
310
                     when start_a =>
311
                        c_state  <= start_b;
312
                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
313
                        isda_oen <= '1';      -- set SDA high
314 31 rherveille
                        sda_chk  <= '0';      -- don't check SDA
315 15 rherveille
 
316 27 rherveille
                     when start_b =>
317
                        c_state  <= start_c;
318
                        iscl_oen <= '1'; -- set SCL high
319
                        isda_oen <= '1'; -- keep SDA high
320 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
321 15 rherveille
 
322 27 rherveille
                     when start_c =>
323
                        c_state  <= start_d;
324
                        iscl_oen <= '1'; -- keep SCL high
325
                        isda_oen <= '0'; -- set SDA low
326 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
327 15 rherveille
 
328 27 rherveille
                     when start_d =>
329
                        c_state  <= start_e;
330
                        iscl_oen <= '1'; -- keep SCL high
331
                        isda_oen <= '0'; -- keep SDA low
332 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
333 15 rherveille
 
334 27 rherveille
                     when start_e =>
335
                        c_state  <= idle;
336
                        cmd_ack  <= '1'; -- command completed
337
                        iscl_oen <= '0'; -- set SCL low
338
                        isda_oen <= '0'; -- keep SDA low
339 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
340 15 rherveille
 
341 27 rherveille
                     -- stop
342
                     when stop_a =>
343
                        c_state  <= stop_b;
344 31 rherveille
                        iscl_oen <= '0'; -- keep SCL low
345 27 rherveille
                        isda_oen <= '0'; -- set SDA low
346 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
347 15 rherveille
 
348 27 rherveille
                     when stop_b =>
349
                        c_state  <= stop_c;
350
                        iscl_oen <= '1'; -- set SCL high
351
                        isda_oen <= '0'; -- keep SDA low
352 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
353 15 rherveille
 
354 27 rherveille
                     when stop_c =>
355
                        c_state  <= stop_d;
356
                        iscl_oen <= '1'; -- keep SCL high
357
                        isda_oen <= '0'; -- keep SDA low
358 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
359 15 rherveille
 
360 27 rherveille
                     when stop_d =>
361
                        c_state  <= idle;
362
                        cmd_ack  <= '1'; -- command completed
363
                        iscl_oen <= '1'; -- keep SCL high
364
                        isda_oen <= '1'; -- set SDA high
365 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
366 15 rherveille
 
367 27 rherveille
                     -- read
368
                     when rd_a =>
369
                        c_state  <= rd_b;
370
                        iscl_oen <= '0'; -- keep SCL low
371
                        isda_oen <= '1'; -- tri-state SDA
372 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
373 15 rherveille
 
374 27 rherveille
                     when rd_b =>
375
                        c_state  <= rd_c;
376
                        iscl_oen <= '1'; -- set SCL high
377
                        isda_oen <= '1'; -- tri-state SDA
378 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
379 15 rherveille
 
380 27 rherveille
                     when rd_c =>
381
                        c_state  <= rd_d;
382
                        iscl_oen <= '1'; -- keep SCL high
383
                        isda_oen <= '1'; -- tri-state SDA
384 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
385 15 rherveille
 
386 27 rherveille
                     when rd_d =>
387
                        c_state  <= idle;
388
                        cmd_ack  <= '1'; -- command completed
389
                        iscl_oen <= '0'; -- set SCL low
390
                        isda_oen <= '1'; -- tri-state SDA
391 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
392 15 rherveille
 
393 27 rherveille
                     -- write
394
                     when wr_a =>
395
                        c_state  <= wr_b;
396
                        iscl_oen <= '0'; -- keep SCL low
397
                        isda_oen <= din; -- set SDA
398 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
399 15 rherveille
 
400 27 rherveille
                     when wr_b =>
401
                        c_state  <= wr_c;
402
                        iscl_oen <= '1'; -- set SCL high
403
                        isda_oen <= din; -- keep SDA
404 31 rherveille
                        sda_chk  <= '1'; -- check SDA
405 15 rherveille
 
406 27 rherveille
                     when wr_c =>
407
                        c_state  <= wr_d;
408
                        iscl_oen <= '1'; -- keep SCL high
409
                        isda_oen <= din; -- keep SDA
410 31 rherveille
                        sda_chk  <= '1'; -- check SDA
411 15 rherveille
 
412 27 rherveille
                     when wr_d =>
413
                        c_state  <= idle;
414
                        cmd_ack  <= '1'; -- command completed
415
                        iscl_oen <= '0'; -- set SCL low
416
                        isda_oen <= din; -- keep SDA
417 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
418 15 rherveille
 
419 27 rherveille
                     when others =>
420 15 rherveille
 
421 27 rherveille
                  end case;
422 24 rherveille
                end if;
423
              end if;
424
            end if;
425 15 rherveille
        end process nxt_state_decoder;
426
 
427
 
428
        -- assign outputs
429
        scl_o   <= '0';
430
        scl_oen <= iscl_oen;
431
        sda_o   <= '0';
432
        sda_oen <= isda_oen;
433
end architecture structural;
434 34 rherveille
 

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