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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Blame information for rev 59

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1 15 rherveille
---------------------------------------------------------------------
2
----                                                             ----
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----  WISHBONE revB2 I2C Master Core; bit-controller             ----
4 15 rherveille
----                                                             ----
5
----                                                             ----
6
----  Author: Richard Herveille                                  ----
7
----          richard@asics.ws                                   ----
8
----          www.asics.ws                                       ----
9
----                                                             ----
10
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
11
----                                                             ----
12
---------------------------------------------------------------------
13
----                                                             ----
14
---- Copyright (C) 2000 Richard Herveille                        ----
15
----                    richard@asics.ws                         ----
16
----                                                             ----
17
---- This source file may be used and distributed without        ----
18
---- restriction provided that this copyright statement is not   ----
19
---- removed from the file and that any derivative work contains ----
20
---- the original copyright notice and the associated disclaimer.----
21
----                                                             ----
22
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
23
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
24
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
25
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
26
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
27
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
28
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
29
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
34
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
36
---------------------------------------------------------------------
37
 
38
--  CVS Log
39
--
40 59 rherveille
--  $Id: i2c_master_bit_ctrl.vhd,v 1.13 2006-10-06 10:48:24 rherveille Exp $
41 15 rherveille
--
42 59 rherveille
--  $Date: 2006-10-06 10:48:24 $
43
--  $Revision: 1.13 $
44 15 rherveille
--  $Author: rherveille $
45
--  $Locker:  $
46
--  $State: Exp $
47
--
48
-- Change History:
49
--               $Log: not supported by cvs2svn $
50 59 rherveille
--               Revision 1.12  2004/05/07 11:53:31  rherveille
51
--               Fixed previous fix :) Made a variable vs signal mistake.
52
--
53 53 rherveille
--               Revision 1.11  2004/05/07 11:04:00  rherveille
54
--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
55
--
56 52 rherveille
--               Revision 1.10  2004/02/27 07:49:43  rherveille
57
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
58
--
59 48 rherveille
--               Revision 1.9  2003/08/12 14:48:37  rherveille
60
--               Forgot an 'end if' :-/
61
--
62 39 rherveille
--               Revision 1.8  2003/08/09 07:01:13  rherveille
63
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
64
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
65
--
66 38 rherveille
--               Revision 1.7  2003/02/05 00:06:02  rherveille
67
--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
68
--
69 35 rherveille
--               Revision 1.6  2003/02/01 02:03:06  rherveille
70
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
71
--
72 34 rherveille
--               Revision 1.5  2002/12/26 16:05:47  rherveille
73
--               Core is now a Multimaster I2C controller.
74
--
75 31 rherveille
--               Revision 1.4  2002/11/30 22:24:37  rherveille
76
--               Cleaned up code
77
--
78 27 rherveille
--               Revision 1.3  2002/10/30 18:09:53  rherveille
79
--               Fixed some reported minor start/stop generation timing issuess.
80
--
81 24 rherveille
--               Revision 1.2  2002/06/15 07:37:04  rherveille
82
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
83
--
84 22 rherveille
--               Revision 1.1  2001/11/05 12:02:33  rherveille
85
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
86
--               Code updated, is now up-to-date to doc. rev.0.4.
87
--               Added headers.
88
--
89 15 rherveille
 
90
 
91
--
92
-------------------------------------
93
-- Bit controller section
94
------------------------------------
95
--
96
-- Translate simple commands into SCL/SDA transitions
97
-- Each command has 5 states, A/B/C/D/idle
98
--
99 31 rherveille
-- start:    SCL  ~~~~~~~~~~~~~~\____
100
--           SDA  XX/~~~~~~~\______
101
--                x | A | B | C | D | i
102 15 rherveille
--
103 31 rherveille
-- repstart  SCL  ______/~~~~~~~\___
104
--           SDA  __/~~~~~~~\______
105
--                x | A | B | C | D | i
106 15 rherveille
--
107 31 rherveille
-- stop      SCL  _______/~~~~~~~~~~~
108
--           SDA  ==\___________/~~~~~
109
--                x | A | B | C | D | i
110 15 rherveille
--
111 31 rherveille
--- write    SCL  ______/~~~~~~~\____
112
--           SDA  XXX===============XX
113
--                x | A | B | C | D | i
114 15 rherveille
--
115 31 rherveille
--- read     SCL  ______/~~~~~~~\____
116
--           SDA  XXXXXXX=XXXXXXXXXXX
117
--                x | A | B | C | D | i
118 15 rherveille
--
119
 
120 24 rherveille
-- Timing:      Normal mode     Fast mode
121 15 rherveille
-----------------------------------------------------------------
122 24 rherveille
-- Fscl         100KHz          400KHz
123
-- Th_scl       4.0us           0.6us   High period of SCL
124
-- Tl_scl       4.7us           1.3us   Low period of SCL
125
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
126
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
127
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
128 15 rherveille
--
129
 
130
library ieee;
131
use ieee.std_logic_1164.all;
132
use ieee.std_logic_arith.all;
133
 
134
entity i2c_master_bit_ctrl is
135
        port (
136
                clk    : in std_logic;
137
                rst    : in std_logic;
138
                nReset : in std_logic;
139
                ena    : in std_logic;                          -- core enable signal
140
 
141
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
142
 
143
                cmd     : in std_logic_vector(3 downto 0);
144 31 rherveille
                cmd_ack : out std_logic; -- command completed
145
                busy    : out std_logic; -- i2c bus busy
146
                al      : out std_logic; -- arbitration lost
147 15 rherveille
 
148
                din  : in std_logic;
149
                dout : out std_logic;
150
 
151
                -- i2c lines
152
                scl_i   : in std_logic;  -- i2c clock line input
153
                scl_o   : out std_logic; -- i2c clock line output
154
                scl_oen : out std_logic; -- i2c clock line output enable, active low
155
                sda_i   : in std_logic;  -- i2c data line input
156
                sda_o   : out std_logic; -- i2c data line output
157
                sda_oen : out std_logic  -- i2c data line output enable, active low
158
        );
159
end entity i2c_master_bit_ctrl;
160
 
161
architecture structural of i2c_master_bit_ctrl is
162 22 rherveille
        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
163
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
164
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
165
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
166
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
167 15 rherveille
 
168 27 rherveille
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
169 24 rherveille
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
170 15 rherveille
        signal c_state : states;
171
 
172 22 rherveille
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
173 31 rherveille
        signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
174
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
175 22 rherveille
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
176 34 rherveille
        signal clk_en, slave_wait : std_logic;          -- clock generation signals
177
        signal ial                : std_logic;          -- internal arbitration lost signal
178 22 rherveille
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
179 15 rherveille
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
180
 
181
begin
182 31 rherveille
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
183 22 rherveille
        -- delay scl_oen
184
        process (clk)
185
        begin
186 24 rherveille
            if (clk'event and clk = '1') then
187 27 rherveille
              dscl_oen <= iscl_oen;
188 24 rherveille
            end if;
189 22 rherveille
        end process;
190
        slave_wait <= dscl_oen and not sSCL;
191 15 rherveille
 
192
        -- generate clk enable signal
193
        gen_clken: process(clk, nReset)
194
        begin
195 24 rherveille
            if (nReset = '0') then
196 27 rherveille
              cnt    <= (others => '0');
197
              clk_en <= '1';
198 24 rherveille
            elsif (clk'event and clk = '1') then
199
              if (rst = '1') then
200 27 rherveille
                cnt    <= (others => '0');
201
                clk_en <= '1';
202 59 rherveille
              elsif ( (cnt = 0) or (ena = '0') ) then
203
                cnt    <= clk_cnt;
204
                clk_en <= '1';
205
              elsif (slave_wait = '1') then
206
                cnt    <= cnt;
207
                clk_en <= '0';
208 24 rherveille
              else
209 59 rherveille
                cnt    <= cnt -1;
210
                clk_en <= '0';
211
              end if
212
            end if
213 15 rherveille
        end process gen_clken;
214
 
215
 
216
        -- generate bus status controller
217
        bus_status_ctrl: block
218 31 rherveille
          signal dSCL, dSDA          : std_logic;  -- delayes sSCL and sSDA
219
          signal sta_condition       : std_logic;  -- start detected
220
          signal sto_condition       : std_logic;  -- stop detected
221 38 rherveille
          signal cmd_stop            : std_logic;  -- STOP command
222 31 rherveille
          signal ibusy               : std_logic;  -- internal busy signal
223
        begin
224
            -- synchronize SCL and SDA inputs
225 35 rherveille
            synch_scl_sda: process(clk, nReset)
226 31 rherveille
            begin
227 35 rherveille
                if (nReset = '0') then
228
                  sSCL <= '1';
229
                  sSDA <= '1';
230 15 rherveille
 
231 35 rherveille
                  dSCL <= '1';
232
                  dSDA <= '1';
233
                elsif (clk'event and clk = '1') then
234
                  if (rst = '1') then
235
                    sSCL <= '1';
236
                    sSDA <= '1';
237
 
238
                    dSCL <= '1';
239
                    dSDA <= '1';
240
                  else
241
                    sSCL <= scl_i;
242
                    sSDA <= sda_i;
243
 
244
                    dSCL <= sSCL;
245
                    dSDA <= sSDA;
246
                  end if;
247 31 rherveille
                end if;
248
            end process synch_SCL_SDA;
249
 
250 24 rherveille
            -- detect start condition => detect falling edge on SDA while SCL is high
251
            -- detect stop condition  => detect rising edge on SDA while SCL is high
252 35 rherveille
            detect_sta_sto: process(clk, nReset)
253 24 rherveille
            begin
254 35 rherveille
                if (nReset = '0') then
255
                  sta_condition <= '0';
256
                  sto_condition <= '0';
257
                elsif (clk'event and clk = '1') then
258
                  if (rst = '1') then
259
                    sta_condition <= '0';
260
                    sto_condition <= '0';
261
                  else
262
                    sta_condition <= (not sSDA and dSDA) and sSCL;
263
                    sto_condition <= (sSDA and not dSDA) and sSCL;
264
                  end if;
265 24 rherveille
                end if;
266
            end process detect_sta_sto;
267 15 rherveille
 
268 31 rherveille
            -- generate i2c-bus busy signal
269 24 rherveille
            gen_busy: process(clk, nReset)
270
            begin
271
                if (nReset = '0') then
272 27 rherveille
                  ibusy <= '0';
273 24 rherveille
                elsif (clk'event and clk = '1') then
274
                  if (rst = '1') then
275 27 rherveille
                    ibusy <= '0';
276 24 rherveille
                  else
277 27 rherveille
                    ibusy <= (sta_condition or ibusy) and not sto_condition;
278 24 rherveille
                  end if;
279
                end if;
280
            end process gen_busy;
281 31 rherveille
            busy <= ibusy;
282 15 rherveille
 
283 31 rherveille
 
284
            -- generate arbitration lost signal
285 52 rherveille
            -- aribitration lost when:
286
            -- 1) master drives SDA high, but the i2c bus is low
287
            -- 2) stop detected while not requested (detect during 'idle' state)
288 35 rherveille
            gen_al: process(clk, nReset)
289 31 rherveille
            begin
290 35 rherveille
              if (nReset = '0') then
291
                cmd_stop  <= '0';
292
                ial       <= '0';
293
              elsif (clk'event and clk = '1') then
294
                if (rst = '1') then
295
                  cmd_stop  <= '0';
296
                  ial       <= '0';
297
                else
298 48 rherveille
                  if (clk_en = '1') then
299 52 rherveille
                    if (cmd = I2C_CMD_STOP) then
300 48 rherveille
                      cmd_stop <= '1';
301
                    else
302
                      cmd_stop <= '0';
303 52 rherveille
                    end if;
304 39 rherveille
                  end if;
305 31 rherveille
 
306 52 rherveille
                  if (c_state = idle) then
307 53 rherveille
                    ial <= (sda_chk and not sSDA and isda_oen);
308 52 rherveille
                  else
309 53 rherveille
                    ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
310 52 rherveille
                  end if;
311
 
312 35 rherveille
                end if;
313 31 rherveille
              end if;
314
            end process gen_al;
315 35 rherveille
            al <= ial;
316 34 rherveille
 
317 31 rherveille
            -- generate dout signal, store dout on rising edge of SCL
318
            gen_dout: process(clk)
319
            begin
320
              if (clk'event and clk = '1') then
321
                if (sSCL = '1' and dSCL = '0') then
322
                  dout <= sSDA;
323
                end if;
324
              end if;
325
            end process gen_dout;
326 15 rherveille
        end block bus_status_ctrl;
327
 
328
 
329
        -- generate statemachine
330
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
331
        begin
332 27 rherveille
            if (nReset = '0') then
333
              c_state  <= idle;
334
              cmd_ack  <= '0';
335
              iscl_oen <= '1';
336
              isda_oen <= '1';
337 31 rherveille
              sda_chk  <= '0';
338 27 rherveille
            elsif (clk'event and clk = '1') then
339 34 rherveille
              if (rst = '1' or ial = '1') then
340 27 rherveille
                c_state  <= idle;
341
                cmd_ack  <= '0';
342
                iscl_oen <= '1';
343
                isda_oen <= '1';
344 31 rherveille
                sda_chk  <= '0';
345 27 rherveille
              else
346
                cmd_ack <= '0'; -- default no acknowledge
347 15 rherveille
 
348 27 rherveille
                if (clk_en = '1') then
349
                  case (c_state) is
350
                     -- idle
351
                     when idle =>
352
                        case cmd is
353
                          when I2C_CMD_START => c_state <= start_a;
354
                          when I2C_CMD_STOP  => c_state <= stop_a;
355
                          when I2C_CMD_WRITE => c_state <= wr_a;
356
                          when I2C_CMD_READ  => c_state <= rd_a;
357
                          when others        => c_state <= idle; -- NOP command
358
                        end case;
359 15 rherveille
 
360 27 rherveille
                        iscl_oen <= iscl_oen; -- keep SCL in same state
361
                        isda_oen <= isda_oen; -- keep SDA in same state
362 31 rherveille
                        sda_chk  <= '0';      -- don't check SDA
363 15 rherveille
 
364 27 rherveille
                     -- start
365
                     when start_a =>
366
                        c_state  <= start_b;
367
                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
368
                        isda_oen <= '1';      -- set SDA high
369 31 rherveille
                        sda_chk  <= '0';      -- don't check SDA
370 15 rherveille
 
371 27 rherveille
                     when start_b =>
372
                        c_state  <= start_c;
373
                        iscl_oen <= '1'; -- set SCL high
374
                        isda_oen <= '1'; -- keep SDA high
375 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
376 15 rherveille
 
377 27 rherveille
                     when start_c =>
378
                        c_state  <= start_d;
379
                        iscl_oen <= '1'; -- keep SCL high
380
                        isda_oen <= '0'; -- set SDA low
381 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
382 15 rherveille
 
383 27 rherveille
                     when start_d =>
384
                        c_state  <= start_e;
385
                        iscl_oen <= '1'; -- keep SCL high
386
                        isda_oen <= '0'; -- keep SDA low
387 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
388 15 rherveille
 
389 27 rherveille
                     when start_e =>
390
                        c_state  <= idle;
391
                        cmd_ack  <= '1'; -- command completed
392
                        iscl_oen <= '0'; -- set SCL low
393
                        isda_oen <= '0'; -- keep SDA low
394 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
395 15 rherveille
 
396 27 rherveille
                     -- stop
397
                     when stop_a =>
398
                        c_state  <= stop_b;
399 31 rherveille
                        iscl_oen <= '0'; -- keep SCL low
400 27 rherveille
                        isda_oen <= '0'; -- set SDA low
401 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
402 15 rherveille
 
403 27 rherveille
                     when stop_b =>
404
                        c_state  <= stop_c;
405
                        iscl_oen <= '1'; -- set SCL high
406
                        isda_oen <= '0'; -- keep SDA low
407 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
408 15 rherveille
 
409 27 rherveille
                     when stop_c =>
410
                        c_state  <= stop_d;
411
                        iscl_oen <= '1'; -- keep SCL high
412
                        isda_oen <= '0'; -- keep SDA low
413 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
414 15 rherveille
 
415 27 rherveille
                     when stop_d =>
416
                        c_state  <= idle;
417
                        cmd_ack  <= '1'; -- command completed
418
                        iscl_oen <= '1'; -- keep SCL high
419
                        isda_oen <= '1'; -- set SDA high
420 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
421 15 rherveille
 
422 27 rherveille
                     -- read
423
                     when rd_a =>
424
                        c_state  <= rd_b;
425
                        iscl_oen <= '0'; -- keep SCL low
426
                        isda_oen <= '1'; -- tri-state SDA
427 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
428 15 rherveille
 
429 27 rherveille
                     when rd_b =>
430
                        c_state  <= rd_c;
431
                        iscl_oen <= '1'; -- set SCL high
432
                        isda_oen <= '1'; -- tri-state SDA
433 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
434 15 rherveille
 
435 27 rherveille
                     when rd_c =>
436
                        c_state  <= rd_d;
437
                        iscl_oen <= '1'; -- keep SCL high
438
                        isda_oen <= '1'; -- tri-state SDA
439 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
440 15 rherveille
 
441 27 rherveille
                     when rd_d =>
442
                        c_state  <= idle;
443
                        cmd_ack  <= '1'; -- command completed
444
                        iscl_oen <= '0'; -- set SCL low
445
                        isda_oen <= '1'; -- tri-state SDA
446 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
447 15 rherveille
 
448 27 rherveille
                     -- write
449
                     when wr_a =>
450
                        c_state  <= wr_b;
451
                        iscl_oen <= '0'; -- keep SCL low
452
                        isda_oen <= din; -- set SDA
453 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
454 15 rherveille
 
455 27 rherveille
                     when wr_b =>
456
                        c_state  <= wr_c;
457
                        iscl_oen <= '1'; -- set SCL high
458
                        isda_oen <= din; -- keep SDA
459 31 rherveille
                        sda_chk  <= '1'; -- check SDA
460 15 rherveille
 
461 27 rherveille
                     when wr_c =>
462
                        c_state  <= wr_d;
463
                        iscl_oen <= '1'; -- keep SCL high
464
                        isda_oen <= din; -- keep SDA
465 31 rherveille
                        sda_chk  <= '1'; -- check SDA
466 15 rherveille
 
467 27 rherveille
                     when wr_d =>
468
                        c_state  <= idle;
469
                        cmd_ack  <= '1'; -- command completed
470
                        iscl_oen <= '0'; -- set SCL low
471
                        isda_oen <= din; -- keep SDA
472 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
473 15 rherveille
 
474 27 rherveille
                     when others =>
475 15 rherveille
 
476 27 rherveille
                  end case;
477 24 rherveille
                end if;
478
              end if;
479
            end if;
480 15 rherveille
        end process nxt_state_decoder;
481
 
482
 
483
        -- assign outputs
484
        scl_o   <= '0';
485
        scl_oen <= iscl_oen;
486
        sda_o   <= '0';
487
        sda_oen <= isda_oen;
488
end architecture structural;
489 34 rherveille
 

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