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---------------------------------------------------------------------
----                                                             ----
----  WISHBONE revB2 I2C Master Core; bit-controller             ----
----                                                             ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2000 Richard Herveille                        ----
----                    richard@asics.ws                         ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
--  CVS Log
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006-10-11 12:10:13 rherveille Exp $
--
--  $Date: 2006-10-11 12:10:13 $
--  $Revision: 1.14 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--               Revision 1.13  2006/10/06 10:48:24  rherveille
--               fixed short scl high pulse after clock stretch
--
--               Revision 1.12  2004/05/07 11:53:31  rherveille
--               Fixed previous fix :) Made a variable vs signal mistake.
--
--               Revision 1.11  2004/05/07 11:04:00  rherveille
--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
--               Revision 1.10  2004/02/27 07:49:43  rherveille
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
--               Revision 1.9  2003/08/12 14:48:37  rherveille
--               Forgot an 'end if' :-/
--
--               Revision 1.8  2003/08/09 07:01:13  rherveille
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
--
--               Revision 1.7  2003/02/05 00:06:02  rherveille
--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
--               Revision 1.6  2003/02/01 02:03:06  rherveille
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
--
--               Revision 1.5  2002/12/26 16:05:47  rherveille
--               Core is now a Multimaster I2C controller.
--
--               Revision 1.4  2002/11/30 22:24:37  rherveille
--               Cleaned up code
--
--               Revision 1.3  2002/10/30 18:09:53  rherveille
--               Fixed some reported minor start/stop generation timing issuess.
--
--               Revision 1.2  2002/06/15 07:37:04  rherveille
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
--               Revision 1.1  2001/11/05 12:02:33  rherveille
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
--               Code updated, is now up-to-date to doc. rev.0.4.
--               Added headers.
--
 
 
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start:    SCL  ~~~~~~~~~~~~~~\____
--           SDA  XX/~~~~~~~\______
--                x | A | B | C | D | i
--
-- repstart  SCL  ______/~~~~~~~\___
--           SDA  __/~~~~~~~\______
--                x | A | B | C | D | i
--
-- stop      SCL  _______/~~~~~~~~~~~
--           SDA  ==\___________/~~~~~
--                x | A | B | C | D | i
--
--- write    SCL  ______/~~~~~~~\____
--           SDA  XXX===============XX
--                x | A | B | C | D | i
--
--- read     SCL  ______/~~~~~~~\____
--           SDA  XXXXXXX=XXXXXXXXXXX
--                x | A | B | C | D | i
--
 
-- Timing:      Normal mode     Fast mode
-----------------------------------------------------------------
-- Fscl         100KHz          400KHz
-- Th_scl       4.0us           0.6us   High period of SCL
-- Tl_scl       4.7us           1.3us   Low period of SCL
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity i2c_master_bit_ctrl is
        port (
                clk    : in std_logic;
                rst    : in std_logic;
                nReset : in std_logic;
                ena    : in std_logic;                          -- core enable signal
 
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
 
                cmd     : in std_logic_vector(3 downto 0);
                cmd_ack : out std_logic; -- command completed
                busy    : out std_logic; -- i2c bus busy
                al      : out std_logic; -- arbitration lost
 
                din  : in std_logic;
                dout : out std_logic;
 
                -- i2c lines
                scl_i   : in std_logic;  -- i2c clock line input
                scl_o   : out std_logic; -- i2c clock line output
                scl_oen : out std_logic; -- i2c clock line output enable, active low
                sda_i   : in std_logic;  -- i2c data line input
                sda_o   : out std_logic; -- i2c data line output
                sda_oen : out std_logic  -- i2c data line output enable, active low
        );
end entity i2c_master_bit_ctrl;
 
architecture structural of i2c_master_bit_ctrl is
        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
 
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
        signal c_state : states;
 
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
        signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
        signal clk_en, slave_wait : std_logic;          -- clock generation signals
        signal ial                : std_logic;          -- internal arbitration lost signal
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
 
begin
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
        -- delay scl_oen
        process (clk)
        begin
            if (clk'event and clk = '1') then
              dscl_oen <= iscl_oen;
            end if;
        end process;
        slave_wait <= dscl_oen and not sSCL;
 
        -- generate clk enable signal
        gen_clken: process(clk, nReset)
        begin
            if (nReset = '0') then
              cnt    <= (others => '0');
              clk_en <= '1';
            elsif (clk'event and clk = '1') then
              if (rst = '1') then
                cnt    <= (others => '0');
                clk_en <= '1';
              elsif ( (cnt = 0) or (ena = '0') ) then
                cnt    <= clk_cnt;
                clk_en <= '1';
              elsif (slave_wait = '1') then
                cnt    <= cnt;
                clk_en <= '0';
              else
                cnt    <= cnt -1;
                clk_en <= '0';
              end if;
            end if;
        end process gen_clken;
 
 
        -- generate bus status controller
        bus_status_ctrl: block
          signal dSCL, dSDA          : std_logic;  -- delayes sSCL and sSDA
          signal sta_condition       : std_logic;  -- start detected
          signal sto_condition       : std_logic;  -- stop detected
          signal cmd_stop            : std_logic;  -- STOP command
          signal ibusy               : std_logic;  -- internal busy signal
        begin
            -- synchronize SCL and SDA inputs
            synch_scl_sda: process(clk, nReset)
            begin
                if (nReset = '0') then
                  sSCL <= '1';
                  sSDA <= '1';
 
                  dSCL <= '1';
                  dSDA <= '1';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    sSCL <= '1';
                    sSDA <= '1';
 
                    dSCL <= '1';
                    dSDA <= '1';
                  else
                    sSCL <= scl_i;
                    sSDA <= sda_i;
 
                    dSCL <= sSCL;
                    dSDA <= sSDA;
                  end if;
                end if;
            end process synch_SCL_SDA;
 
            -- detect start condition => detect falling edge on SDA while SCL is high
            -- detect stop condition  => detect rising edge on SDA while SCL is high
            detect_sta_sto: process(clk, nReset)
            begin
                if (nReset = '0') then
                  sta_condition <= '0';
                  sto_condition <= '0';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    sta_condition <= '0';
                    sto_condition <= '0';
                  else
                    sta_condition <= (not sSDA and dSDA) and sSCL;
                    sto_condition <= (sSDA and not dSDA) and sSCL;
                  end if;
                end if;
            end process detect_sta_sto;
 
            -- generate i2c-bus busy signal
            gen_busy: process(clk, nReset)
            begin
                if (nReset = '0') then
                  ibusy <= '0';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    ibusy <= '0';
                  else
                    ibusy <= (sta_condition or ibusy) and not sto_condition;
                  end if;
                end if;
            end process gen_busy;
            busy <= ibusy;
 
 
            -- generate arbitration lost signal
            -- aribitration lost when:
            -- 1) master drives SDA high, but the i2c bus is low
            -- 2) stop detected while not requested (detect during 'idle' state)
            gen_al: process(clk, nReset)
            begin
              if (nReset = '0') then
                cmd_stop  <= '0';
                ial       <= '0';
              elsif (clk'event and clk = '1') then
                if (rst = '1') then
                  cmd_stop  <= '0';
                  ial       <= '0';
                else
                  if (clk_en = '1') then
                    if (cmd = I2C_CMD_STOP) then
                      cmd_stop <= '1';
                    else
                      cmd_stop <= '0';
                    end if;
                  end if;
 
                  if (c_state = idle) then
                    ial <= (sda_chk and not sSDA and isda_oen);
                  else
                    ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
                  end if;
 
                end if;
              end if;
            end process gen_al;
            al <= ial;
 
            -- generate dout signal, store dout on rising edge of SCL
            gen_dout: process(clk)
            begin
              if (clk'event and clk = '1') then
                if (sSCL = '1' and dSCL = '0') then
                  dout <= sSDA;
                end if;
              end if;
            end process gen_dout;
        end block bus_status_ctrl;
 
 
        -- generate statemachine
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
        begin
            if (nReset = '0') then
              c_state  <= idle;
              cmd_ack  <= '0';
              iscl_oen <= '1';
              isda_oen <= '1';
              sda_chk  <= '0';
            elsif (clk'event and clk = '1') then
              if (rst = '1' or ial = '1') then
                c_state  <= idle;
                cmd_ack  <= '0';
                iscl_oen <= '1';
                isda_oen <= '1';
                sda_chk  <= '0';
              else
                cmd_ack <= '0'; -- default no acknowledge
 
                if (clk_en = '1') then
                  case (c_state) is
                     -- idle
                     when idle =>
                        case cmd is
                          when I2C_CMD_START => c_state <= start_a;
                          when I2C_CMD_STOP  => c_state <= stop_a;
                          when I2C_CMD_WRITE => c_state <= wr_a;
                          when I2C_CMD_READ  => c_state <= rd_a;
                          when others        => c_state <= idle; -- NOP command
                        end case;
 
                        iscl_oen <= iscl_oen; -- keep SCL in same state
                        isda_oen <= isda_oen; -- keep SDA in same state
                        sda_chk  <= '0';      -- don't check SDA
 
                     -- start
                     when start_a =>
                        c_state  <= start_b;
                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
                        isda_oen <= '1';      -- set SDA high
                        sda_chk  <= '0';      -- don't check SDA
 
                     when start_b =>
                        c_state  <= start_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '1'; -- keep SDA high
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_c =>
                        c_state  <= start_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- set SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_d =>
                        c_state  <= start_e;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_e =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- stop
                     when stop_a =>
                        c_state  <= stop_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= '0'; -- set SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_b =>
                        c_state  <= stop_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_c =>
                        c_state  <= stop_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '1'; -- set SDA high
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- read
                     when rd_a =>
                        c_state  <= rd_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_b =>
                        c_state  <= rd_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_c =>
                        c_state  <= rd_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- write
                     when wr_a =>
                        c_state  <= wr_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= din; -- set SDA
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
 
                     when wr_b =>
                        c_state  <= wr_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '1'; -- check SDA
 
                     when wr_c =>
                        c_state  <= wr_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '1'; -- check SDA
 
                     when wr_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
 
                     when others =>
 
                  end case;
                end if;
              end if;
            end if;
        end process nxt_state_decoder;
 
 
        -- assign outputs
        scl_o   <= '0';
        scl_oen <= iscl_oen;
        sda_o   <= '0';
        sda_oen <= isda_oen;
end architecture structural;
 

Line No.	Rev	Author	Line
1	15	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3	27	rherveille	`---- WISHBONE revB2 I2C Master Core; bit-controller ----`
4	15	rherveille	`---- ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---- Downloaded from: http://www.opencores.org/projects/i2c/ ----`
11			`---- ----`
12			`---------------------------------------------------------------------`
13			`---- ----`
14			`---- Copyright (C) 2000 Richard Herveille ----`
15			`---- richard@asics.ws ----`
16			`---- ----`
17			`---- This source file may be used and distributed without ----`
18			`---- restriction provided that this copyright statement is not ----`
19			`---- removed from the file and that any derivative work contains ----`
20			`---- the original copyright notice and the associated disclaimer.----`
21			`---- ----`
22			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
23			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
24			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
25			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
26			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
27			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
28			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
29			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
30			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
31			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
32			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
33			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
34			`---- POSSIBILITY OF SUCH DAMAGE. ----`
35			`---- ----`
36			`---------------------------------------------------------------------`
37
38			`-- CVS Log`
39			`--`
40	60	rherveille	`-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006-10-11 12:10:13 rherveille Exp $`
41	15	rherveille	`--`
42	60	rherveille	`-- $Date: 2006-10-11 12:10:13 $`
43			`-- $Revision: 1.14 $`
44	15	rherveille	`-- $Author: rherveille $`
45			`-- $Locker: $`
46			`-- $State: Exp $`
47			`--`
48			`-- Change History:`
49			`-- $Log: not supported by cvs2svn $`
50	60	rherveille	`-- Revision 1.13 2006/10/06 10:48:24 rherveille`
51			`-- fixed short scl high pulse after clock stretch`
52			`--`
53	59	rherveille	`-- Revision 1.12 2004/05/07 11:53:31 rherveille`
54			`-- Fixed previous fix :) Made a variable vs signal mistake.`
55			`--`
56	53	rherveille	`-- Revision 1.11 2004/05/07 11:04:00 rherveille`
57			`-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.`
58			`--`
59	52	rherveille	`-- Revision 1.10 2004/02/27 07:49:43 rherveille`
60			`-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.`
61			`--`
62	48	rherveille	`-- Revision 1.9 2003/08/12 14:48:37 rherveille`
63			`-- Forgot an 'end if' :-/`
64			`--`
65	39	rherveille	`-- Revision 1.8 2003/08/09 07:01:13 rherveille`
66			`-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.`
67			`-- Fixed a potential bug in the byte controller's host-acknowledge generation.`
68			`--`
69	38	rherveille	`-- Revision 1.7 2003/02/05 00:06:02 rherveille`
70			`-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.`
71			`--`
72	35	rherveille	`-- Revision 1.6 2003/02/01 02:03:06 rherveille`
73			`-- Fixed a few 'arbitration lost' bugs. VHDL version only.`
74			`--`
75	34	rherveille	`-- Revision 1.5 2002/12/26 16:05:47 rherveille`
76			`-- Core is now a Multimaster I2C controller.`
77			`--`
78	31	rherveille	`-- Revision 1.4 2002/11/30 22:24:37 rherveille`
79			`-- Cleaned up code`
80			`--`
81	27	rherveille	`-- Revision 1.3 2002/10/30 18:09:53 rherveille`
82			`-- Fixed some reported minor start/stop generation timing issuess.`
83			`--`
84	24	rherveille	`-- Revision 1.2 2002/06/15 07:37:04 rherveille`
85			`-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.`
86			`--`
87	22	rherveille	`-- Revision 1.1 2001/11/05 12:02:33 rherveille`
88			`-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.`
89			`-- Code updated, is now up-to-date to doc. rev.0.4.`
90			`-- Added headers.`
91			`--`
92	15	rherveille
93
94			`--`
95			`-------------------------------------`
96			`-- Bit controller section`
97			`------------------------------------`
98			`--`
99			`-- Translate simple commands into SCL/SDA transitions`
100			`-- Each command has 5 states, A/B/C/D/idle`
101			`--`
102	31	rherveille	`-- start: SCL ~~~~~~~~~~~~~~\____`
103			`-- SDA XX/~~~~~~~\______`
104			`-- x \| A \| B \| C \| D \| i`
105	15	rherveille	`--`
106	31	rherveille	`-- repstart SCL ______/~~~~~~~\___`
107			`-- SDA __/~~~~~~~\______`
108			`-- x \| A \| B \| C \| D \| i`
109	15	rherveille	`--`
110	31	rherveille	`-- stop SCL _______/~~~~~~~~~~~`
111			`-- SDA ==\___________/~~~~~`
112			`-- x \| A \| B \| C \| D \| i`
113	15	rherveille	`--`
114	31	rherveille	`--- write SCL ______/~~~~~~~\____`
115			`-- SDA XXX===============XX`
116			`-- x \| A \| B \| C \| D \| i`
117	15	rherveille	`--`
118	31	rherveille	`--- read SCL ______/~~~~~~~\____`
119			`-- SDA XXXXXXX=XXXXXXXXXXX`
120			`-- x \| A \| B \| C \| D \| i`
121	15	rherveille	`--`
122
123	24	rherveille	`-- Timing: Normal mode Fast mode`
124	15	rherveille	`-----------------------------------------------------------------`
125	24	rherveille	`-- Fscl 100KHz 400KHz`
126			`-- Th_scl 4.0us 0.6us High period of SCL`
127			`-- Tl_scl 4.7us 1.3us Low period of SCL`
128			`-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition`
129			`-- Tsu:sto 4.0us 0.6us setup time for a stop conditon`
130			`-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition`
131	15	rherveille	`--`
132
133			`library ieee;`
134			`use ieee.std_logic_1164.all;`
135			`use ieee.std_logic_arith.all;`
136
137			`entity i2c_master_bit_ctrl is`
138			`port (`
139			`clk : in std_logic;`
140			`rst : in std_logic;`
141			`nReset : in std_logic;`
142			`ena : in std_logic; -- core enable signal`
143
144			`clk_cnt : in unsigned(15 downto 0); -- clock prescale value`
145
146			`cmd : in std_logic_vector(3 downto 0);`
147	31	rherveille	`cmd_ack : out std_logic; -- command completed`
148			`busy : out std_logic; -- i2c bus busy`
149			`al : out std_logic; -- arbitration lost`
150	15	rherveille
151			`din : in std_logic;`
152			`dout : out std_logic;`
153
154			`-- i2c lines`
155			`scl_i : in std_logic; -- i2c clock line input`
156			`scl_o : out std_logic; -- i2c clock line output`
157			`scl_oen : out std_logic; -- i2c clock line output enable, active low`
158			`sda_i : in std_logic; -- i2c data line input`
159			`sda_o : out std_logic; -- i2c data line output`
160			`sda_oen : out std_logic -- i2c data line output enable, active low`
161			`);`
162			`end entity i2c_master_bit_ctrl;`
163
164			`architecture structural of i2c_master_bit_ctrl is`
165	22	rherveille	`constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";`
166			`constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";`
167			`constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";`
168			`constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";`
169			`constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";`
170	15	rherveille
171	27	rherveille	`type states is (idle, start_a, start_b, start_c, start_d, start_e,`
172	24	rherveille	`stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);`
173	15	rherveille	`signal c_state : states;`
174
175	22	rherveille	`signal iscl_oen, isda_oen : std_logic; -- internal I2C lines`
176	31	rherveille	`signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)`
177			`signal dscl_oen : std_logic; -- delayed scl_oen signals`
178	22	rherveille	`signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs`
179	34	rherveille	`signal clk_en, slave_wait : std_logic; -- clock generation signals`
180			`signal ial : std_logic; -- internal arbitration lost signal`
181	22	rherveille	`-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)`
182	15	rherveille	`signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)`
183
184			`begin`
185	31	rherveille	`-- whenever the slave is not ready it can delay the cycle by pulling SCL low`
186	22	rherveille	`-- delay scl_oen`
187			`process (clk)`
188			`begin`
189	24	rherveille	`if (clk'event and clk = '1') then`
190	27	rherveille	`dscl_oen <= iscl_oen;`
191	24	rherveille	`end if;`
192	22	rherveille	`end process;`
193			`slave_wait <= dscl_oen and not sSCL;`
194	15	rherveille
195			`-- generate clk enable signal`
196			`gen_clken: process(clk, nReset)`
197			`begin`
198	24	rherveille	`if (nReset = '0') then`
199	27	rherveille	`cnt <= (others => '0');`
200			`clk_en <= '1';`
201	24	rherveille	`elsif (clk'event and clk = '1') then`
202			`if (rst = '1') then`
203	27	rherveille	`cnt <= (others => '0');`
204			`clk_en <= '1';`
205	59	rherveille	`elsif ( (cnt = 0) or (ena = '0') ) then`
206			`cnt <= clk_cnt;`
207			`clk_en <= '1';`
208			`elsif (slave_wait = '1') then`
209			`cnt <= cnt;`
210			`clk_en <= '0';`
211	24	rherveille	`else`
212	59	rherveille	`cnt <= cnt -1;`
213			`clk_en <= '0';`
214	60	rherveille	`end if;`
215			`end if;`
216	15	rherveille	`end process gen_clken;`
217
218
219			`-- generate bus status controller`
220			`bus_status_ctrl: block`
221	31	rherveille	`signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA`
222			`signal sta_condition : std_logic; -- start detected`
223			`signal sto_condition : std_logic; -- stop detected`
224	38	rherveille	`signal cmd_stop : std_logic; -- STOP command`
225	31	rherveille	`signal ibusy : std_logic; -- internal busy signal`
226			`begin`
227			`-- synchronize SCL and SDA inputs`
228	35	rherveille	`synch_scl_sda: process(clk, nReset)`
229	31	rherveille	`begin`
230	35	rherveille	`if (nReset = '0') then`
231			`sSCL <= '1';`
232			`sSDA <= '1';`
233	15	rherveille
234	35	rherveille	`dSCL <= '1';`
235			`dSDA <= '1';`
236			`elsif (clk'event and clk = '1') then`
237			`if (rst = '1') then`
238			`sSCL <= '1';`
239			`sSDA <= '1';`
240
241			`dSCL <= '1';`
242			`dSDA <= '1';`
243			`else`
244			`sSCL <= scl_i;`
245			`sSDA <= sda_i;`
246
247			`dSCL <= sSCL;`
248			`dSDA <= sSDA;`
249			`end if;`
250	31	rherveille	`end if;`
251			`end process synch_SCL_SDA;`
252
253	24	rherveille	`-- detect start condition => detect falling edge on SDA while SCL is high`
254			`-- detect stop condition => detect rising edge on SDA while SCL is high`
255	35	rherveille	`detect_sta_sto: process(clk, nReset)`
256	24	rherveille	`begin`
257	35	rherveille	`if (nReset = '0') then`
258			`sta_condition <= '0';`
259			`sto_condition <= '0';`
260			`elsif (clk'event and clk = '1') then`
261			`if (rst = '1') then`
262			`sta_condition <= '0';`
263			`sto_condition <= '0';`
264			`else`
265			`sta_condition <= (not sSDA and dSDA) and sSCL;`
266			`sto_condition <= (sSDA and not dSDA) and sSCL;`
267			`end if;`
268	24	rherveille	`end if;`
269			`end process detect_sta_sto;`
270	15	rherveille
271	31	rherveille	`-- generate i2c-bus busy signal`
272	24	rherveille	`gen_busy: process(clk, nReset)`
273			`begin`
274			`if (nReset = '0') then`
275	27	rherveille	`ibusy <= '0';`
276	24	rherveille	`elsif (clk'event and clk = '1') then`
277			`if (rst = '1') then`
278	27	rherveille	`ibusy <= '0';`
279	24	rherveille	`else`
280	27	rherveille	`ibusy <= (sta_condition or ibusy) and not sto_condition;`
281	24	rherveille	`end if;`
282			`end if;`
283			`end process gen_busy;`
284	31	rherveille	`busy <= ibusy;`
285	15	rherveille
286	31	rherveille
287			`-- generate arbitration lost signal`
288	52	rherveille	`-- aribitration lost when:`
289			`-- 1) master drives SDA high, but the i2c bus is low`
290			`-- 2) stop detected while not requested (detect during 'idle' state)`
291	35	rherveille	`gen_al: process(clk, nReset)`
292	31	rherveille	`begin`
293	35	rherveille	`if (nReset = '0') then`
294			`cmd_stop <= '0';`
295			`ial <= '0';`
296			`elsif (clk'event and clk = '1') then`
297			`if (rst = '1') then`
298			`cmd_stop <= '0';`
299			`ial <= '0';`
300			`else`
301	48	rherveille	`if (clk_en = '1') then`
302	52	rherveille	`if (cmd = I2C_CMD_STOP) then`
303	48	rherveille	`cmd_stop <= '1';`
304			`else`
305			`cmd_stop <= '0';`
306	52	rherveille	`end if;`
307	39	rherveille	`end if;`
308	31	rherveille
309	52	rherveille	`if (c_state = idle) then`
310	53	rherveille	`ial <= (sda_chk and not sSDA and isda_oen);`
311	52	rherveille	`else`
312	53	rherveille	`ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);`
313	52	rherveille	`end if;`
314
315	35	rherveille	`end if;`
316	31	rherveille	`end if;`
317			`end process gen_al;`
318	35	rherveille	`al <= ial;`
319	34	rherveille
320	31	rherveille	`-- generate dout signal, store dout on rising edge of SCL`
321			`gen_dout: process(clk)`
322			`begin`
323			`if (clk'event and clk = '1') then`
324			`if (sSCL = '1' and dSCL = '0') then`
325			`dout <= sSDA;`
326			`end if;`
327			`end if;`
328			`end process gen_dout;`
329	15	rherveille	`end block bus_status_ctrl;`
330
331
332			`-- generate statemachine`
333			`nxt_state_decoder : process (clk, nReset, c_state, cmd)`
334			`begin`
335	27	rherveille	`if (nReset = '0') then`
336			`c_state <= idle;`
337			`cmd_ack <= '0';`
338			`iscl_oen <= '1';`
339			`isda_oen <= '1';`
340	31	rherveille	`sda_chk <= '0';`
341	27	rherveille	`elsif (clk'event and clk = '1') then`
342	34	rherveille	`if (rst = '1' or ial = '1') then`
343	27	rherveille	`c_state <= idle;`
344			`cmd_ack <= '0';`
345			`iscl_oen <= '1';`
346			`isda_oen <= '1';`
347	31	rherveille	`sda_chk <= '0';`
348	27	rherveille	`else`
349			`cmd_ack <= '0'; -- default no acknowledge`
350	15	rherveille
351	27	rherveille	`if (clk_en = '1') then`
352			`case (c_state) is`
353			`-- idle`
354			`when idle =>`
355			`case cmd is`
356			`when I2C_CMD_START => c_state <= start_a;`
357			`when I2C_CMD_STOP => c_state <= stop_a;`
358			`when I2C_CMD_WRITE => c_state <= wr_a;`
359			`when I2C_CMD_READ => c_state <= rd_a;`
360			`when others => c_state <= idle; -- NOP command`
361			`end case;`
362	15	rherveille
363	27	rherveille	`iscl_oen <= iscl_oen; -- keep SCL in same state`
364			`isda_oen <= isda_oen; -- keep SDA in same state`
365	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
366	15	rherveille
367	27	rherveille	`-- start`
368			`when start_a =>`
369			`c_state <= start_b;`
370			`iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)`
371			`isda_oen <= '1'; -- set SDA high`
372	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
373	15	rherveille
374	27	rherveille	`when start_b =>`
375			`c_state <= start_c;`
376			`iscl_oen <= '1'; -- set SCL high`
377			`isda_oen <= '1'; -- keep SDA high`
378	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
379	15	rherveille
380	27	rherveille	`when start_c =>`
381			`c_state <= start_d;`
382			`iscl_oen <= '1'; -- keep SCL high`
383			`isda_oen <= '0'; -- set SDA low`
384	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
385	15	rherveille
386	27	rherveille	`when start_d =>`
387			`c_state <= start_e;`
388			`iscl_oen <= '1'; -- keep SCL high`
389			`isda_oen <= '0'; -- keep SDA low`
390	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
391	15	rherveille
392	27	rherveille	`when start_e =>`
393			`c_state <= idle;`
394			`cmd_ack <= '1'; -- command completed`
395			`iscl_oen <= '0'; -- set SCL low`
396			`isda_oen <= '0'; -- keep SDA low`
397	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
398	15	rherveille
399	27	rherveille	`-- stop`
400			`when stop_a =>`
401			`c_state <= stop_b;`
402	31	rherveille	`iscl_oen <= '0'; -- keep SCL low`
403	27	rherveille	`isda_oen <= '0'; -- set SDA low`
404	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
405	15	rherveille
406	27	rherveille	`when stop_b =>`
407			`c_state <= stop_c;`
408			`iscl_oen <= '1'; -- set SCL high`
409			`isda_oen <= '0'; -- keep SDA low`
410	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
411	15	rherveille
412	27	rherveille	`when stop_c =>`
413			`c_state <= stop_d;`
414			`iscl_oen <= '1'; -- keep SCL high`
415			`isda_oen <= '0'; -- keep SDA low`
416	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
417	15	rherveille
418	27	rherveille	`when stop_d =>`
419			`c_state <= idle;`
420			`cmd_ack <= '1'; -- command completed`
421			`iscl_oen <= '1'; -- keep SCL high`
422			`isda_oen <= '1'; -- set SDA high`
423	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
424	15	rherveille
425	27	rherveille	`-- read`
426			`when rd_a =>`
427			`c_state <= rd_b;`
428			`iscl_oen <= '0'; -- keep SCL low`
429			`isda_oen <= '1'; -- tri-state SDA`
430	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
431	15	rherveille
432	27	rherveille	`when rd_b =>`
433			`c_state <= rd_c;`
434			`iscl_oen <= '1'; -- set SCL high`
435			`isda_oen <= '1'; -- tri-state SDA`
436	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
437	15	rherveille
438	27	rherveille	`when rd_c =>`
439			`c_state <= rd_d;`
440			`iscl_oen <= '1'; -- keep SCL high`
441			`isda_oen <= '1'; -- tri-state SDA`
442	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
443	15	rherveille
444	27	rherveille	`when rd_d =>`
445			`c_state <= idle;`
446			`cmd_ack <= '1'; -- command completed`
447			`iscl_oen <= '0'; -- set SCL low`
448			`isda_oen <= '1'; -- tri-state SDA`
449	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
450	15	rherveille
451	27	rherveille	`-- write`
452			`when wr_a =>`
453			`c_state <= wr_b;`
454			`iscl_oen <= '0'; -- keep SCL low`
455			`isda_oen <= din; -- set SDA`
456	31	rherveille	`sda_chk <= '0'; -- don't check SDA (SCL low)`
457	15	rherveille
458	27	rherveille	`when wr_b =>`
459			`c_state <= wr_c;`
460			`iscl_oen <= '1'; -- set SCL high`
461			`isda_oen <= din; -- keep SDA`
462	31	rherveille	`sda_chk <= '1'; -- check SDA`
463	15	rherveille
464	27	rherveille	`when wr_c =>`
465			`c_state <= wr_d;`
466			`iscl_oen <= '1'; -- keep SCL high`
467			`isda_oen <= din; -- keep SDA`
468	31	rherveille	`sda_chk <= '1'; -- check SDA`
469	15	rherveille
470	27	rherveille	`when wr_d =>`
471			`c_state <= idle;`
472			`cmd_ack <= '1'; -- command completed`
473			`iscl_oen <= '0'; -- set SCL low`
474			`isda_oen <= din; -- keep SDA`
475	31	rherveille	`sda_chk <= '0'; -- don't check SDA (SCL low)`
476	15	rherveille
477	27	rherveille	`when others =>`
478	15	rherveille
479	27	rherveille	`end case;`
480	24	rherveille	`end if;`
481			`end if;`
482			`end if;`
483	15	rherveille	`end process nxt_state_decoder;`
484
485
486			`-- assign outputs`
487			`scl_o <= '0';`
488			`scl_oen <= iscl_oen;`
489			`sda_o <= '0';`
490			`sda_oen <= isda_oen;`
491			`end architecture structural;`
492	34	rherveille

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