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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Blame information for rev 66

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1 15 rherveille
---------------------------------------------------------------------
2
----                                                             ----
3 27 rherveille
----  WISHBONE revB2 I2C Master Core; bit-controller             ----
4 15 rherveille
----                                                             ----
5
----                                                             ----
6
----  Author: Richard Herveille                                  ----
7
----          richard@asics.ws                                   ----
8
----          www.asics.ws                                       ----
9
----                                                             ----
10
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
11
----                                                             ----
12
---------------------------------------------------------------------
13
----                                                             ----
14
---- Copyright (C) 2000 Richard Herveille                        ----
15
----                    richard@asics.ws                         ----
16
----                                                             ----
17
---- This source file may be used and distributed without        ----
18
---- restriction provided that this copyright statement is not   ----
19
---- removed from the file and that any derivative work contains ----
20
---- the original copyright notice and the associated disclaimer.----
21
----                                                             ----
22
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
23
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
24
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
25
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
26
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
27
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
28
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
29
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
30
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
31
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
32
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
33
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
34
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
35
----                                                             ----
36
---------------------------------------------------------------------
37
 
38
--  CVS Log
39
--
40 66 rherveille
--  $Id: i2c_master_bit_ctrl.vhd,v 1.16 2009-01-20 20:40:36 rherveille Exp $
41 15 rherveille
--
42 66 rherveille
--  $Date: 2009-01-20 20:40:36 $
43
--  $Revision: 1.16 $
44 15 rherveille
--  $Author: rherveille $
45
--  $Locker:  $
46
--  $State: Exp $
47
--
48
-- Change History:
49
--               $Log: not supported by cvs2svn $
50 66 rherveille
--               Revision 1.15  2009/01/20 10:34:51  rherveille
51
--               Added SCL clock synchronization logic
52
--               Fixed slave_wait signal generation
53
--
54 64 rherveille
--               Revision 1.14  2006/10/11 12:10:13  rherveille
55
--               Added missing semicolons ';' on endif
56
--
57 60 rherveille
--               Revision 1.13  2006/10/06 10:48:24  rherveille
58
--               fixed short scl high pulse after clock stretch
59
--
60 59 rherveille
--               Revision 1.12  2004/05/07 11:53:31  rherveille
61
--               Fixed previous fix :) Made a variable vs signal mistake.
62
--
63 53 rherveille
--               Revision 1.11  2004/05/07 11:04:00  rherveille
64
--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
65
--
66 52 rherveille
--               Revision 1.10  2004/02/27 07:49:43  rherveille
67
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
68
--
69 48 rherveille
--               Revision 1.9  2003/08/12 14:48:37  rherveille
70
--               Forgot an 'end if' :-/
71
--
72 39 rherveille
--               Revision 1.8  2003/08/09 07:01:13  rherveille
73
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
74
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
75
--
76 38 rherveille
--               Revision 1.7  2003/02/05 00:06:02  rherveille
77
--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
78
--
79 35 rherveille
--               Revision 1.6  2003/02/01 02:03:06  rherveille
80
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
81
--
82 34 rherveille
--               Revision 1.5  2002/12/26 16:05:47  rherveille
83
--               Core is now a Multimaster I2C controller.
84
--
85 31 rherveille
--               Revision 1.4  2002/11/30 22:24:37  rherveille
86
--               Cleaned up code
87
--
88 27 rherveille
--               Revision 1.3  2002/10/30 18:09:53  rherveille
89
--               Fixed some reported minor start/stop generation timing issuess.
90
--
91 24 rherveille
--               Revision 1.2  2002/06/15 07:37:04  rherveille
92
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
93
--
94 22 rherveille
--               Revision 1.1  2001/11/05 12:02:33  rherveille
95
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
96
--               Code updated, is now up-to-date to doc. rev.0.4.
97
--               Added headers.
98
--
99 15 rherveille
 
100
 
101
--
102
-------------------------------------
103
-- Bit controller section
104
------------------------------------
105
--
106
-- Translate simple commands into SCL/SDA transitions
107
-- Each command has 5 states, A/B/C/D/idle
108
--
109 31 rherveille
-- start:    SCL  ~~~~~~~~~~~~~~\____
110
--           SDA  XX/~~~~~~~\______
111
--                x | A | B | C | D | i
112 15 rherveille
--
113 31 rherveille
-- repstart  SCL  ______/~~~~~~~\___
114
--           SDA  __/~~~~~~~\______
115
--                x | A | B | C | D | i
116 15 rherveille
--
117 31 rherveille
-- stop      SCL  _______/~~~~~~~~~~~
118
--           SDA  ==\___________/~~~~~
119
--                x | A | B | C | D | i
120 15 rherveille
--
121 31 rherveille
--- write    SCL  ______/~~~~~~~\____
122
--           SDA  XXX===============XX
123
--                x | A | B | C | D | i
124 15 rherveille
--
125 31 rherveille
--- read     SCL  ______/~~~~~~~\____
126
--           SDA  XXXXXXX=XXXXXXXXXXX
127
--                x | A | B | C | D | i
128 15 rherveille
--
129
 
130 24 rherveille
-- Timing:      Normal mode     Fast mode
131 15 rherveille
-----------------------------------------------------------------
132 24 rherveille
-- Fscl         100KHz          400KHz
133
-- Th_scl       4.0us           0.6us   High period of SCL
134
-- Tl_scl       4.7us           1.3us   Low period of SCL
135
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
136
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
137
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
138 15 rherveille
--
139
 
140
library ieee;
141
use ieee.std_logic_1164.all;
142
use ieee.std_logic_arith.all;
143
 
144
entity i2c_master_bit_ctrl is
145
        port (
146
                clk    : in std_logic;
147
                rst    : in std_logic;
148
                nReset : in std_logic;
149
                ena    : in std_logic;                          -- core enable signal
150
 
151
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
152
 
153
                cmd     : in std_logic_vector(3 downto 0);
154 31 rherveille
                cmd_ack : out std_logic; -- command completed
155
                busy    : out std_logic; -- i2c bus busy
156
                al      : out std_logic; -- arbitration lost
157 15 rherveille
 
158
                din  : in std_logic;
159
                dout : out std_logic;
160
 
161
                -- i2c lines
162
                scl_i   : in std_logic;  -- i2c clock line input
163
                scl_o   : out std_logic; -- i2c clock line output
164
                scl_oen : out std_logic; -- i2c clock line output enable, active low
165
                sda_i   : in std_logic;  -- i2c data line input
166
                sda_o   : out std_logic; -- i2c data line output
167
                sda_oen : out std_logic  -- i2c data line output enable, active low
168
        );
169
end entity i2c_master_bit_ctrl;
170
 
171
architecture structural of i2c_master_bit_ctrl is
172 22 rherveille
        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
173
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
174
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
175
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
176
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
177 15 rherveille
 
178 27 rherveille
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
179 24 rherveille
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
180 15 rherveille
        signal c_state : states;
181
 
182 64 rherveille
        signal iscl_oen, isda_oen   : std_logic;        -- internal I2C lines
183
        signal sda_chk              : std_logic;        -- check SDA status (multi-master arbitration)
184
        signal dscl_oen             : std_logic;        -- delayed scl_oen signals
185
        signal sSCL, sSDA           : std_logic;        -- synchronized SCL and SDA inputs
186
        signal dSCL, dSDA           : std_logic;        -- delayed versions ofsSCL and sSDA
187
        signal clk_en               : std_logic;        -- statemachine clock enable
188
        signal scl_sync, slave_wait : std_logic;        -- clock generation signals
189
        signal ial                  : std_logic;        -- internal arbitration lost signal
190 22 rherveille
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
191 15 rherveille
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
192
 
193
begin
194 31 rherveille
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
195 22 rherveille
        -- delay scl_oen
196
        process (clk)
197
        begin
198 24 rherveille
            if (clk'event and clk = '1') then
199 27 rherveille
              dscl_oen <= iscl_oen;
200 24 rherveille
            end if;
201 22 rherveille
        end process;
202 15 rherveille
 
203 64 rherveille
        -- slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low
204
        -- slave_wait remains asserted until the slave (other master) releases SCL
205
        process (clk, nReset)
206
        begin
207
            if (nReset = '0') then
208
              slave_wait <= '0';
209
            else
210 66 rherveille
              slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
211 64 rherveille
            end if;
212
        end process;
213
 
214
        -- master drives SCL high, but another master pulls it low
215
        -- master start counting down its low cycle now (clock synchronization)
216 66 rherveille
        scl_sync <= dSCL and not sSCL and iscl_oen;
217 64 rherveille
 
218 15 rherveille
        -- generate clk enable signal
219
        gen_clken: process(clk, nReset)
220
        begin
221 24 rherveille
            if (nReset = '0') then
222 27 rherveille
              cnt    <= (others => '0');
223
              clk_en <= '1';
224 24 rherveille
            elsif (clk'event and clk = '1') then
225
              if (rst = '1') then
226 27 rherveille
                cnt    <= (others => '0');
227
                clk_en <= '1';
228 64 rherveille
              elsif ( (cnt = 0) or (ena = '0') or (scl_sync = '1') ) then
229 59 rherveille
                cnt    <= clk_cnt;
230
                clk_en <= '1';
231
              elsif (slave_wait = '1') then
232
                cnt    <= cnt;
233
                clk_en <= '0';
234 24 rherveille
              else
235 59 rherveille
                cnt    <= cnt -1;
236
                clk_en <= '0';
237 60 rherveille
              end if;
238
            end if;
239 15 rherveille
        end process gen_clken;
240
 
241
 
242
        -- generate bus status controller
243
        bus_status_ctrl: block
244 31 rherveille
          signal sta_condition       : std_logic;  -- start detected
245
          signal sto_condition       : std_logic;  -- stop detected
246 38 rherveille
          signal cmd_stop            : std_logic;  -- STOP command
247 31 rherveille
          signal ibusy               : std_logic;  -- internal busy signal
248
        begin
249
            -- synchronize SCL and SDA inputs
250 35 rherveille
            synch_scl_sda: process(clk, nReset)
251 31 rherveille
            begin
252 35 rherveille
                if (nReset = '0') then
253
                  sSCL <= '1';
254
                  sSDA <= '1';
255 15 rherveille
 
256 35 rherveille
                  dSCL <= '1';
257
                  dSDA <= '1';
258
                elsif (clk'event and clk = '1') then
259
                  if (rst = '1') then
260
                    sSCL <= '1';
261
                    sSDA <= '1';
262
 
263
                    dSCL <= '1';
264
                    dSDA <= '1';
265
                  else
266
                    sSCL <= scl_i;
267
                    sSDA <= sda_i;
268
 
269
                    dSCL <= sSCL;
270
                    dSDA <= sSDA;
271
                  end if;
272 31 rherveille
                end if;
273
            end process synch_SCL_SDA;
274
 
275 24 rherveille
            -- detect start condition => detect falling edge on SDA while SCL is high
276
            -- detect stop condition  => detect rising edge on SDA while SCL is high
277 35 rherveille
            detect_sta_sto: process(clk, nReset)
278 24 rherveille
            begin
279 35 rherveille
                if (nReset = '0') then
280
                  sta_condition <= '0';
281
                  sto_condition <= '0';
282
                elsif (clk'event and clk = '1') then
283
                  if (rst = '1') then
284
                    sta_condition <= '0';
285
                    sto_condition <= '0';
286
                  else
287
                    sta_condition <= (not sSDA and dSDA) and sSCL;
288
                    sto_condition <= (sSDA and not dSDA) and sSCL;
289
                  end if;
290 24 rherveille
                end if;
291
            end process detect_sta_sto;
292 15 rherveille
 
293 31 rherveille
            -- generate i2c-bus busy signal
294 24 rherveille
            gen_busy: process(clk, nReset)
295
            begin
296
                if (nReset = '0') then
297 27 rherveille
                  ibusy <= '0';
298 24 rherveille
                elsif (clk'event and clk = '1') then
299
                  if (rst = '1') then
300 27 rherveille
                    ibusy <= '0';
301 24 rherveille
                  else
302 27 rherveille
                    ibusy <= (sta_condition or ibusy) and not sto_condition;
303 24 rherveille
                  end if;
304
                end if;
305
            end process gen_busy;
306 31 rherveille
            busy <= ibusy;
307 15 rherveille
 
308 31 rherveille
 
309
            -- generate arbitration lost signal
310 52 rherveille
            -- aribitration lost when:
311
            -- 1) master drives SDA high, but the i2c bus is low
312
            -- 2) stop detected while not requested (detect during 'idle' state)
313 35 rherveille
            gen_al: process(clk, nReset)
314 31 rherveille
            begin
315 35 rherveille
              if (nReset = '0') then
316
                cmd_stop  <= '0';
317
                ial       <= '0';
318
              elsif (clk'event and clk = '1') then
319
                if (rst = '1') then
320
                  cmd_stop  <= '0';
321
                  ial       <= '0';
322
                else
323 48 rherveille
                  if (clk_en = '1') then
324 52 rherveille
                    if (cmd = I2C_CMD_STOP) then
325 48 rherveille
                      cmd_stop <= '1';
326
                    else
327
                      cmd_stop <= '0';
328 52 rherveille
                    end if;
329 39 rherveille
                  end if;
330 31 rherveille
 
331 52 rherveille
                  if (c_state = idle) then
332 53 rherveille
                    ial <= (sda_chk and not sSDA and isda_oen);
333 52 rherveille
                  else
334 53 rherveille
                    ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
335 52 rherveille
                  end if;
336
 
337 35 rherveille
                end if;
338 31 rherveille
              end if;
339
            end process gen_al;
340 35 rherveille
            al <= ial;
341 34 rherveille
 
342 31 rherveille
            -- generate dout signal, store dout on rising edge of SCL
343
            gen_dout: process(clk)
344
            begin
345
              if (clk'event and clk = '1') then
346
                if (sSCL = '1' and dSCL = '0') then
347
                  dout <= sSDA;
348
                end if;
349
              end if;
350
            end process gen_dout;
351 15 rherveille
        end block bus_status_ctrl;
352
 
353
 
354
        -- generate statemachine
355
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
356
        begin
357 27 rherveille
            if (nReset = '0') then
358
              c_state  <= idle;
359
              cmd_ack  <= '0';
360
              iscl_oen <= '1';
361
              isda_oen <= '1';
362 31 rherveille
              sda_chk  <= '0';
363 27 rherveille
            elsif (clk'event and clk = '1') then
364 34 rherveille
              if (rst = '1' or ial = '1') then
365 27 rherveille
                c_state  <= idle;
366
                cmd_ack  <= '0';
367
                iscl_oen <= '1';
368
                isda_oen <= '1';
369 31 rherveille
                sda_chk  <= '0';
370 27 rherveille
              else
371
                cmd_ack <= '0'; -- default no acknowledge
372 15 rherveille
 
373 27 rherveille
                if (clk_en = '1') then
374
                  case (c_state) is
375
                     -- idle
376
                     when idle =>
377
                        case cmd is
378
                          when I2C_CMD_START => c_state <= start_a;
379
                          when I2C_CMD_STOP  => c_state <= stop_a;
380
                          when I2C_CMD_WRITE => c_state <= wr_a;
381
                          when I2C_CMD_READ  => c_state <= rd_a;
382
                          when others        => c_state <= idle; -- NOP command
383
                        end case;
384 15 rherveille
 
385 27 rherveille
                        iscl_oen <= iscl_oen; -- keep SCL in same state
386
                        isda_oen <= isda_oen; -- keep SDA in same state
387 31 rherveille
                        sda_chk  <= '0';      -- don't check SDA
388 15 rherveille
 
389 27 rherveille
                     -- start
390
                     when start_a =>
391
                        c_state  <= start_b;
392
                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
393
                        isda_oen <= '1';      -- set SDA high
394 31 rherveille
                        sda_chk  <= '0';      -- don't check SDA
395 15 rherveille
 
396 27 rherveille
                     when start_b =>
397
                        c_state  <= start_c;
398
                        iscl_oen <= '1'; -- set SCL high
399
                        isda_oen <= '1'; -- keep SDA high
400 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
401 15 rherveille
 
402 27 rherveille
                     when start_c =>
403
                        c_state  <= start_d;
404
                        iscl_oen <= '1'; -- keep SCL high
405
                        isda_oen <= '0'; -- set SDA low
406 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
407 15 rherveille
 
408 27 rherveille
                     when start_d =>
409
                        c_state  <= start_e;
410
                        iscl_oen <= '1'; -- keep SCL high
411
                        isda_oen <= '0'; -- keep SDA low
412 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
413 15 rherveille
 
414 27 rherveille
                     when start_e =>
415
                        c_state  <= idle;
416
                        cmd_ack  <= '1'; -- command completed
417
                        iscl_oen <= '0'; -- set SCL low
418
                        isda_oen <= '0'; -- keep SDA low
419 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
420 15 rherveille
 
421 27 rherveille
                     -- stop
422
                     when stop_a =>
423
                        c_state  <= stop_b;
424 31 rherveille
                        iscl_oen <= '0'; -- keep SCL low
425 27 rherveille
                        isda_oen <= '0'; -- set SDA low
426 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
427 15 rherveille
 
428 27 rherveille
                     when stop_b =>
429
                        c_state  <= stop_c;
430
                        iscl_oen <= '1'; -- set SCL high
431
                        isda_oen <= '0'; -- keep SDA low
432 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
433 15 rherveille
 
434 27 rherveille
                     when stop_c =>
435
                        c_state  <= stop_d;
436
                        iscl_oen <= '1'; -- keep SCL high
437
                        isda_oen <= '0'; -- keep SDA low
438 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
439 15 rherveille
 
440 27 rherveille
                     when stop_d =>
441
                        c_state  <= idle;
442
                        cmd_ack  <= '1'; -- command completed
443
                        iscl_oen <= '1'; -- keep SCL high
444
                        isda_oen <= '1'; -- set SDA high
445 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
446 15 rherveille
 
447 27 rherveille
                     -- read
448
                     when rd_a =>
449
                        c_state  <= rd_b;
450
                        iscl_oen <= '0'; -- keep SCL low
451
                        isda_oen <= '1'; -- tri-state SDA
452 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
453 15 rherveille
 
454 27 rherveille
                     when rd_b =>
455
                        c_state  <= rd_c;
456
                        iscl_oen <= '1'; -- set SCL high
457
                        isda_oen <= '1'; -- tri-state SDA
458 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
459 15 rherveille
 
460 27 rherveille
                     when rd_c =>
461
                        c_state  <= rd_d;
462
                        iscl_oen <= '1'; -- keep SCL high
463
                        isda_oen <= '1'; -- tri-state SDA
464 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
465 15 rherveille
 
466 27 rherveille
                     when rd_d =>
467
                        c_state  <= idle;
468
                        cmd_ack  <= '1'; -- command completed
469
                        iscl_oen <= '0'; -- set SCL low
470
                        isda_oen <= '1'; -- tri-state SDA
471 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
472 15 rherveille
 
473 27 rherveille
                     -- write
474
                     when wr_a =>
475
                        c_state  <= wr_b;
476
                        iscl_oen <= '0'; -- keep SCL low
477
                        isda_oen <= din; -- set SDA
478 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
479 15 rherveille
 
480 27 rherveille
                     when wr_b =>
481
                        c_state  <= wr_c;
482
                        iscl_oen <= '1'; -- set SCL high
483
                        isda_oen <= din; -- keep SDA
484 31 rherveille
                        sda_chk  <= '1'; -- check SDA
485 15 rherveille
 
486 27 rherveille
                     when wr_c =>
487
                        c_state  <= wr_d;
488
                        iscl_oen <= '1'; -- keep SCL high
489
                        isda_oen <= din; -- keep SDA
490 31 rherveille
                        sda_chk  <= '1'; -- check SDA
491 15 rherveille
 
492 27 rherveille
                     when wr_d =>
493
                        c_state  <= idle;
494
                        cmd_ack  <= '1'; -- command completed
495
                        iscl_oen <= '0'; -- set SCL low
496
                        isda_oen <= din; -- keep SDA
497 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
498 15 rherveille
 
499 27 rherveille
                     when others =>
500 15 rherveille
 
501 27 rherveille
                  end case;
502 24 rherveille
                end if;
503
              end if;
504
            end if;
505 15 rherveille
        end process nxt_state_decoder;
506
 
507
 
508
        -- assign outputs
509
        scl_o   <= '0';
510
        scl_oen <= iscl_oen;
511
        sda_o   <= '0';
512
        sda_oen <= isda_oen;
513
end architecture structural;
514 34 rherveille
 

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