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---------------------------------------------------------------------
----                                                             ----
----  WISHBONE revB2 I2C Master Core; bit-controller             ----
----                                                             ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2000 Richard Herveille                        ----
----                    richard@asics.ws                         ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
--  CVS Log
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
--
--  $Date: 2009-02-04 20:17:34 $
--  $Revision: 1.17 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--               Revision 1.16  2009/01/20 20:40:36  rherveille
--               Fixed type iscl_oen instead of scl_oen
--
--               Revision 1.15  2009/01/20 10:34:51  rherveille
--               Added SCL clock synchronization logic
--               Fixed slave_wait signal generation
--
--               Revision 1.14  2006/10/11 12:10:13  rherveille
--               Added missing semicolons ';' on endif
--
--               Revision 1.13  2006/10/06 10:48:24  rherveille
--               fixed short scl high pulse after clock stretch
--
--               Revision 1.12  2004/05/07 11:53:31  rherveille
--               Fixed previous fix :) Made a variable vs signal mistake.
--
--               Revision 1.11  2004/05/07 11:04:00  rherveille
--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
--               Revision 1.10  2004/02/27 07:49:43  rherveille
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
--               Revision 1.9  2003/08/12 14:48:37  rherveille
--               Forgot an 'end if' :-/
--
--               Revision 1.8  2003/08/09 07:01:13  rherveille
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
--
--               Revision 1.7  2003/02/05 00:06:02  rherveille
--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
--               Revision 1.6  2003/02/01 02:03:06  rherveille
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
--
--               Revision 1.5  2002/12/26 16:05:47  rherveille
--               Core is now a Multimaster I2C controller.
--
--               Revision 1.4  2002/11/30 22:24:37  rherveille
--               Cleaned up code
--
--               Revision 1.3  2002/10/30 18:09:53  rherveille
--               Fixed some reported minor start/stop generation timing issuess.
--
--               Revision 1.2  2002/06/15 07:37:04  rherveille
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
--               Revision 1.1  2001/11/05 12:02:33  rherveille
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
--               Code updated, is now up-to-date to doc. rev.0.4.
--               Added headers.
--
 
 
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start:    SCL  ~~~~~~~~~~~~~~\____
--           SDA  XX/~~~~~~~\______
--                x | A | B | C | D | i
--
-- repstart  SCL  ______/~~~~~~~\___
--           SDA  __/~~~~~~~\______
--                x | A | B | C | D | i
--
-- stop      SCL  _______/~~~~~~~~~~~
--           SDA  ==\___________/~~~~~
--                x | A | B | C | D | i
--
--- write    SCL  ______/~~~~~~~\____
--           SDA  XXX===============XX
--                x | A | B | C | D | i
--
--- read     SCL  ______/~~~~~~~\____
--           SDA  XXXXXXX=XXXXXXXXXXX
--                x | A | B | C | D | i
--
 
-- Timing:      Normal mode     Fast mode
-----------------------------------------------------------------
-- Fscl         100KHz          400KHz
-- Th_scl       4.0us           0.6us   High period of SCL
-- Tl_scl       4.7us           1.3us   Low period of SCL
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity i2c_master_bit_ctrl is
        port (
                clk    : in std_logic;
                rst    : in std_logic;
                nReset : in std_logic;
                ena    : in std_logic;                          -- core enable signal
 
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
 
                cmd     : in std_logic_vector(3 downto 0);
                cmd_ack : out std_logic; -- command completed
                busy    : out std_logic; -- i2c bus busy
                al      : out std_logic; -- arbitration lost
 
                din  : in std_logic;
                dout : out std_logic;
 
                -- i2c lines
                scl_i   : in std_logic;  -- i2c clock line input
                scl_o   : out std_logic; -- i2c clock line output
                scl_oen : out std_logic; -- i2c clock line output enable, active low
                sda_i   : in std_logic;  -- i2c data line input
                sda_o   : out std_logic; -- i2c data line output
                sda_oen : out std_logic  -- i2c data line output enable, active low
        );
end entity i2c_master_bit_ctrl;
 
architecture structural of i2c_master_bit_ctrl is
        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
 
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
        signal c_state : states;
 
        signal iscl_oen, isda_oen   : std_logic;        -- internal I2C lines
        signal sda_chk              : std_logic;        -- check SDA status (multi-master arbitration)
        signal dscl_oen             : std_logic;        -- delayed scl_oen signals
        signal sSCL, sSDA           : std_logic;        -- synchronized SCL and SDA inputs
        signal dSCL, dSDA           : std_logic;        -- delayed versions ofsSCL and sSDA
        signal clk_en               : std_logic;        -- statemachine clock enable
        signal scl_sync, slave_wait : std_logic;        -- clock generation signals
        signal ial                  : std_logic;        -- internal arbitration lost signal
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
 
begin
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
        -- delay scl_oen
        process (clk)
        begin
            if (clk'event and clk = '1') then
              dscl_oen <= iscl_oen;
            end if;
        end process;
 
        -- slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low
        -- slave_wait remains asserted until the slave (other master) releases SCL
        process (clk, nReset)
        begin
            if (nReset = '0') then
              slave_wait <= '0';
            elsif (clk'event and clk = '1') then
              slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
            end if;
        end process;
 
        -- master drives SCL high, but another master pulls it low
        -- master start counting down its low cycle now (clock synchronization)
        scl_sync <= dSCL and not sSCL and iscl_oen;
 
        -- generate clk enable signal
        gen_clken: process(clk, nReset)
        begin
            if (nReset = '0') then
              cnt    <= (others => '0');
              clk_en <= '1';
            elsif (clk'event and clk = '1') then
              if (rst = '1') then
                cnt    <= (others => '0');
                clk_en <= '1';
              elsif ( (cnt = 0) or (ena = '0') or (scl_sync = '1') ) then
                cnt    <= clk_cnt;
                clk_en <= '1';
              elsif (slave_wait = '1') then
                cnt    <= cnt;
                clk_en <= '0';
              else
                cnt    <= cnt -1;
                clk_en <= '0';
              end if;
            end if;
        end process gen_clken;
 
 
        -- generate bus status controller
        bus_status_ctrl: block
          signal sta_condition       : std_logic;  -- start detected
          signal sto_condition       : std_logic;  -- stop detected
          signal cmd_stop            : std_logic;  -- STOP command
          signal ibusy               : std_logic;  -- internal busy signal
        begin
            -- synchronize SCL and SDA inputs
            synch_scl_sda: process(clk, nReset)
            begin
                if (nReset = '0') then
                  sSCL <= '1';
                  sSDA <= '1';
 
                  dSCL <= '1';
                  dSDA <= '1';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    sSCL <= '1';
                    sSDA <= '1';
 
                    dSCL <= '1';
                    dSDA <= '1';
                  else
                    sSCL <= scl_i;
                    sSDA <= sda_i;
 
                    dSCL <= sSCL;
                    dSDA <= sSDA;
                  end if;
                end if;
            end process synch_SCL_SDA;
 
            -- detect start condition => detect falling edge on SDA while SCL is high
            -- detect stop condition  => detect rising edge on SDA while SCL is high
            detect_sta_sto: process(clk, nReset)
            begin
                if (nReset = '0') then
                  sta_condition <= '0';
                  sto_condition <= '0';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    sta_condition <= '0';
                    sto_condition <= '0';
                  else
                    sta_condition <= (not sSDA and dSDA) and sSCL;
                    sto_condition <= (sSDA and not dSDA) and sSCL;
                  end if;
                end if;
            end process detect_sta_sto;
 
            -- generate i2c-bus busy signal
            gen_busy: process(clk, nReset)
            begin
                if (nReset = '0') then
                  ibusy <= '0';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    ibusy <= '0';
                  else
                    ibusy <= (sta_condition or ibusy) and not sto_condition;
                  end if;
                end if;
            end process gen_busy;
            busy <= ibusy;
 
 
            -- generate arbitration lost signal
            -- aribitration lost when:
            -- 1) master drives SDA high, but the i2c bus is low
            -- 2) stop detected while not requested (detect during 'idle' state)
            gen_al: process(clk, nReset)
            begin
              if (nReset = '0') then
                cmd_stop  <= '0';
                ial       <= '0';
              elsif (clk'event and clk = '1') then
                if (rst = '1') then
                  cmd_stop  <= '0';
                  ial       <= '0';
                else
                  if (clk_en = '1') then
                    if (cmd = I2C_CMD_STOP) then
                      cmd_stop <= '1';
                    else
                      cmd_stop <= '0';
                    end if;
                  end if;
 
                  if (c_state = idle) then
                    ial <= (sda_chk and not sSDA and isda_oen);
                  else
                    ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
                  end if;
 
                end if;
              end if;
            end process gen_al;
            al <= ial;
 
            -- generate dout signal, store dout on rising edge of SCL
            gen_dout: process(clk)
            begin
              if (clk'event and clk = '1') then
                if (sSCL = '1' and dSCL = '0') then
                  dout <= sSDA;
                end if;
              end if;
            end process gen_dout;
        end block bus_status_ctrl;
 
 
        -- generate statemachine
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
        begin
            if (nReset = '0') then
              c_state  <= idle;
              cmd_ack  <= '0';
              iscl_oen <= '1';
              isda_oen <= '1';
              sda_chk  <= '0';
            elsif (clk'event and clk = '1') then
              if (rst = '1' or ial = '1') then
                c_state  <= idle;
                cmd_ack  <= '0';
                iscl_oen <= '1';
                isda_oen <= '1';
                sda_chk  <= '0';
              else
                cmd_ack <= '0'; -- default no acknowledge
 
                if (clk_en = '1') then
                  case (c_state) is
                     -- idle
                     when idle =>
                        case cmd is
                          when I2C_CMD_START => c_state <= start_a;
                          when I2C_CMD_STOP  => c_state <= stop_a;
                          when I2C_CMD_WRITE => c_state <= wr_a;
                          when I2C_CMD_READ  => c_state <= rd_a;
                          when others        => c_state <= idle; -- NOP command
                        end case;
 
                        iscl_oen <= iscl_oen; -- keep SCL in same state
                        isda_oen <= isda_oen; -- keep SDA in same state
                        sda_chk  <= '0';      -- don't check SDA
 
                     -- start
                     when start_a =>
                        c_state  <= start_b;
                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
                        isda_oen <= '1';      -- set SDA high
                        sda_chk  <= '0';      -- don't check SDA
 
                     when start_b =>
                        c_state  <= start_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '1'; -- keep SDA high
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_c =>
                        c_state  <= start_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- set SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_d =>
                        c_state  <= start_e;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_e =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- stop
                     when stop_a =>
                        c_state  <= stop_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= '0'; -- set SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_b =>
                        c_state  <= stop_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_c =>
                        c_state  <= stop_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '1'; -- set SDA high
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- read
                     when rd_a =>
                        c_state  <= rd_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_b =>
                        c_state  <= rd_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_c =>
                        c_state  <= rd_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- write
                     when wr_a =>
                        c_state  <= wr_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= din; -- set SDA
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
 
                     when wr_b =>
                        c_state  <= wr_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '1'; -- check SDA
 
                     when wr_c =>
                        c_state  <= wr_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '1'; -- check SDA
 
                     when wr_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
 
                     when others =>
 
                  end case;
                end if;
              end if;
            end if;
        end process nxt_state_decoder;
 
 
        -- assign outputs
        scl_o   <= '0';
        scl_oen <= iscl_oen;
        sda_o   <= '0';
        sda_oen <= isda_oen;
end architecture structural;
 

Line No.	Rev	Author	Line
1	15	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3	27	rherveille	`---- WISHBONE revB2 I2C Master Core; bit-controller ----`
4	15	rherveille	`---- ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---- Downloaded from: http://www.opencores.org/projects/i2c/ ----`
11			`---- ----`
12			`---------------------------------------------------------------------`
13			`---- ----`
14			`---- Copyright (C) 2000 Richard Herveille ----`
15			`---- richard@asics.ws ----`
16			`---- ----`
17			`---- This source file may be used and distributed without ----`
18			`---- restriction provided that this copyright statement is not ----`
19			`---- removed from the file and that any derivative work contains ----`
20			`---- the original copyright notice and the associated disclaimer.----`
21			`---- ----`
22			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
23			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
24			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
25			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
26			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
27			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
28			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
29			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
30			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
31			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
32			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
33			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
34			`---- POSSIBILITY OF SUCH DAMAGE. ----`
35			`---- ----`
36			`---------------------------------------------------------------------`
37
38			`-- CVS Log`
39			`--`
40	67	rherveille	`-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $`
41	15	rherveille	`--`
42	67	rherveille	`-- $Date: 2009-02-04 20:17:34 $`
43			`-- $Revision: 1.17 $`
44	15	rherveille	`-- $Author: rherveille $`
45			`-- $Locker: $`
46			`-- $State: Exp $`
47			`--`
48			`-- Change History:`
49			`-- $Log: not supported by cvs2svn $`
50	67	rherveille	`-- Revision 1.16 2009/01/20 20:40:36 rherveille`
51			`-- Fixed type iscl_oen instead of scl_oen`
52			`--`
53	66	rherveille	`-- Revision 1.15 2009/01/20 10:34:51 rherveille`
54			`-- Added SCL clock synchronization logic`
55			`-- Fixed slave_wait signal generation`
56			`--`
57	64	rherveille	`-- Revision 1.14 2006/10/11 12:10:13 rherveille`
58			`-- Added missing semicolons ';' on endif`
59			`--`
60	60	rherveille	`-- Revision 1.13 2006/10/06 10:48:24 rherveille`
61			`-- fixed short scl high pulse after clock stretch`
62			`--`
63	59	rherveille	`-- Revision 1.12 2004/05/07 11:53:31 rherveille`
64			`-- Fixed previous fix :) Made a variable vs signal mistake.`
65			`--`
66	53	rherveille	`-- Revision 1.11 2004/05/07 11:04:00 rherveille`
67			`-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.`
68			`--`
69	52	rherveille	`-- Revision 1.10 2004/02/27 07:49:43 rherveille`
70			`-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.`
71			`--`
72	48	rherveille	`-- Revision 1.9 2003/08/12 14:48:37 rherveille`
73			`-- Forgot an 'end if' :-/`
74			`--`
75	39	rherveille	`-- Revision 1.8 2003/08/09 07:01:13 rherveille`
76			`-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.`
77			`-- Fixed a potential bug in the byte controller's host-acknowledge generation.`
78			`--`
79	38	rherveille	`-- Revision 1.7 2003/02/05 00:06:02 rherveille`
80			`-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.`
81			`--`
82	35	rherveille	`-- Revision 1.6 2003/02/01 02:03:06 rherveille`
83			`-- Fixed a few 'arbitration lost' bugs. VHDL version only.`
84			`--`
85	34	rherveille	`-- Revision 1.5 2002/12/26 16:05:47 rherveille`
86			`-- Core is now a Multimaster I2C controller.`
87			`--`
88	31	rherveille	`-- Revision 1.4 2002/11/30 22:24:37 rherveille`
89			`-- Cleaned up code`
90			`--`
91	27	rherveille	`-- Revision 1.3 2002/10/30 18:09:53 rherveille`
92			`-- Fixed some reported minor start/stop generation timing issuess.`
93			`--`
94	24	rherveille	`-- Revision 1.2 2002/06/15 07:37:04 rherveille`
95			`-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.`
96			`--`
97	22	rherveille	`-- Revision 1.1 2001/11/05 12:02:33 rherveille`
98			`-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.`
99			`-- Code updated, is now up-to-date to doc. rev.0.4.`
100			`-- Added headers.`
101			`--`
102	15	rherveille
103
104			`--`
105			`-------------------------------------`
106			`-- Bit controller section`
107			`------------------------------------`
108			`--`
109			`-- Translate simple commands into SCL/SDA transitions`
110			`-- Each command has 5 states, A/B/C/D/idle`
111			`--`
112	31	rherveille	`-- start: SCL ~~~~~~~~~~~~~~\____`
113			`-- SDA XX/~~~~~~~\______`
114			`-- x \| A \| B \| C \| D \| i`
115	15	rherveille	`--`
116	31	rherveille	`-- repstart SCL ______/~~~~~~~\___`
117			`-- SDA __/~~~~~~~\______`
118			`-- x \| A \| B \| C \| D \| i`
119	15	rherveille	`--`
120	31	rherveille	`-- stop SCL _______/~~~~~~~~~~~`
121			`-- SDA ==\___________/~~~~~`
122			`-- x \| A \| B \| C \| D \| i`
123	15	rherveille	`--`
124	31	rherveille	`--- write SCL ______/~~~~~~~\____`
125			`-- SDA XXX===============XX`
126			`-- x \| A \| B \| C \| D \| i`
127	15	rherveille	`--`
128	31	rherveille	`--- read SCL ______/~~~~~~~\____`
129			`-- SDA XXXXXXX=XXXXXXXXXXX`
130			`-- x \| A \| B \| C \| D \| i`
131	15	rherveille	`--`
132
133	24	rherveille	`-- Timing: Normal mode Fast mode`
134	15	rherveille	`-----------------------------------------------------------------`
135	24	rherveille	`-- Fscl 100KHz 400KHz`
136			`-- Th_scl 4.0us 0.6us High period of SCL`
137			`-- Tl_scl 4.7us 1.3us Low period of SCL`
138			`-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition`
139			`-- Tsu:sto 4.0us 0.6us setup time for a stop conditon`
140			`-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition`
141	15	rherveille	`--`
142
143			`library ieee;`
144			`use ieee.std_logic_1164.all;`
145			`use ieee.std_logic_arith.all;`
146
147			`entity i2c_master_bit_ctrl is`
148			`port (`
149			`clk : in std_logic;`
150			`rst : in std_logic;`
151			`nReset : in std_logic;`
152			`ena : in std_logic; -- core enable signal`
153
154			`clk_cnt : in unsigned(15 downto 0); -- clock prescale value`
155
156			`cmd : in std_logic_vector(3 downto 0);`
157	31	rherveille	`cmd_ack : out std_logic; -- command completed`
158			`busy : out std_logic; -- i2c bus busy`
159			`al : out std_logic; -- arbitration lost`
160	15	rherveille
161			`din : in std_logic;`
162			`dout : out std_logic;`
163
164			`-- i2c lines`
165			`scl_i : in std_logic; -- i2c clock line input`
166			`scl_o : out std_logic; -- i2c clock line output`
167			`scl_oen : out std_logic; -- i2c clock line output enable, active low`
168			`sda_i : in std_logic; -- i2c data line input`
169			`sda_o : out std_logic; -- i2c data line output`
170			`sda_oen : out std_logic -- i2c data line output enable, active low`
171			`);`
172			`end entity i2c_master_bit_ctrl;`
173
174			`architecture structural of i2c_master_bit_ctrl is`
175	22	rherveille	`constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";`
176			`constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";`
177			`constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";`
178			`constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";`
179			`constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";`
180	15	rherveille
181	27	rherveille	`type states is (idle, start_a, start_b, start_c, start_d, start_e,`
182	24	rherveille	`stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);`
183	15	rherveille	`signal c_state : states;`
184
185	64	rherveille	`signal iscl_oen, isda_oen : std_logic; -- internal I2C lines`
186			`signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)`
187			`signal dscl_oen : std_logic; -- delayed scl_oen signals`
188			`signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs`
189			`signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA`
190			`signal clk_en : std_logic; -- statemachine clock enable`
191			`signal scl_sync, slave_wait : std_logic; -- clock generation signals`
192			`signal ial : std_logic; -- internal arbitration lost signal`
193	22	rherveille	`-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)`
194	15	rherveille	`signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)`
195
196			`begin`
197	31	rherveille	`-- whenever the slave is not ready it can delay the cycle by pulling SCL low`
198	22	rherveille	`-- delay scl_oen`
199			`process (clk)`
200			`begin`
201	24	rherveille	`if (clk'event and clk = '1') then`
202	27	rherveille	`dscl_oen <= iscl_oen;`
203	24	rherveille	`end if;`
204	22	rherveille	`end process;`
205	15	rherveille
206	64	rherveille	`-- slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low`
207			`-- slave_wait remains asserted until the slave (other master) releases SCL`
208			`process (clk, nReset)`
209			`begin`
210			`if (nReset = '0') then`
211			`slave_wait <= '0';`
212	67	rherveille	`elsif (clk'event and clk = '1') then`
213	66	rherveille	`slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);`
214	64	rherveille	`end if;`
215			`end process;`
216
217			`-- master drives SCL high, but another master pulls it low`
218			`-- master start counting down its low cycle now (clock synchronization)`
219	66	rherveille	`scl_sync <= dSCL and not sSCL and iscl_oen;`
220	64	rherveille
221	15	rherveille	`-- generate clk enable signal`
222			`gen_clken: process(clk, nReset)`
223			`begin`
224	24	rherveille	`if (nReset = '0') then`
225	27	rherveille	`cnt <= (others => '0');`
226			`clk_en <= '1';`
227	24	rherveille	`elsif (clk'event and clk = '1') then`
228			`if (rst = '1') then`
229	27	rherveille	`cnt <= (others => '0');`
230			`clk_en <= '1';`
231	64	rherveille	`elsif ( (cnt = 0) or (ena = '0') or (scl_sync = '1') ) then`
232	59	rherveille	`cnt <= clk_cnt;`
233			`clk_en <= '1';`
234			`elsif (slave_wait = '1') then`
235			`cnt <= cnt;`
236			`clk_en <= '0';`
237	24	rherveille	`else`
238	59	rherveille	`cnt <= cnt -1;`
239			`clk_en <= '0';`
240	60	rherveille	`end if;`
241			`end if;`
242	15	rherveille	`end process gen_clken;`
243
244
245			`-- generate bus status controller`
246			`bus_status_ctrl: block`
247	31	rherveille	`signal sta_condition : std_logic; -- start detected`
248			`signal sto_condition : std_logic; -- stop detected`
249	38	rherveille	`signal cmd_stop : std_logic; -- STOP command`
250	31	rherveille	`signal ibusy : std_logic; -- internal busy signal`
251			`begin`
252			`-- synchronize SCL and SDA inputs`
253	35	rherveille	`synch_scl_sda: process(clk, nReset)`
254	31	rherveille	`begin`
255	35	rherveille	`if (nReset = '0') then`
256			`sSCL <= '1';`
257			`sSDA <= '1';`
258	15	rherveille
259	35	rherveille	`dSCL <= '1';`
260			`dSDA <= '1';`
261			`elsif (clk'event and clk = '1') then`
262			`if (rst = '1') then`
263			`sSCL <= '1';`
264			`sSDA <= '1';`
265
266			`dSCL <= '1';`
267			`dSDA <= '1';`
268			`else`
269			`sSCL <= scl_i;`
270			`sSDA <= sda_i;`
271
272			`dSCL <= sSCL;`
273			`dSDA <= sSDA;`
274			`end if;`
275	31	rherveille	`end if;`
276			`end process synch_SCL_SDA;`
277
278	24	rherveille	`-- detect start condition => detect falling edge on SDA while SCL is high`
279			`-- detect stop condition => detect rising edge on SDA while SCL is high`
280	35	rherveille	`detect_sta_sto: process(clk, nReset)`
281	24	rherveille	`begin`
282	35	rherveille	`if (nReset = '0') then`
283			`sta_condition <= '0';`
284			`sto_condition <= '0';`
285			`elsif (clk'event and clk = '1') then`
286			`if (rst = '1') then`
287			`sta_condition <= '0';`
288			`sto_condition <= '0';`
289			`else`
290			`sta_condition <= (not sSDA and dSDA) and sSCL;`
291			`sto_condition <= (sSDA and not dSDA) and sSCL;`
292			`end if;`
293	24	rherveille	`end if;`
294			`end process detect_sta_sto;`
295	15	rherveille
296	31	rherveille	`-- generate i2c-bus busy signal`
297	24	rherveille	`gen_busy: process(clk, nReset)`
298			`begin`
299			`if (nReset = '0') then`
300	27	rherveille	`ibusy <= '0';`
301	24	rherveille	`elsif (clk'event and clk = '1') then`
302			`if (rst = '1') then`
303	27	rherveille	`ibusy <= '0';`
304	24	rherveille	`else`
305	27	rherveille	`ibusy <= (sta_condition or ibusy) and not sto_condition;`
306	24	rherveille	`end if;`
307			`end if;`
308			`end process gen_busy;`
309	31	rherveille	`busy <= ibusy;`
310	15	rherveille
311	31	rherveille
312			`-- generate arbitration lost signal`
313	52	rherveille	`-- aribitration lost when:`
314			`-- 1) master drives SDA high, but the i2c bus is low`
315			`-- 2) stop detected while not requested (detect during 'idle' state)`
316	35	rherveille	`gen_al: process(clk, nReset)`
317	31	rherveille	`begin`
318	35	rherveille	`if (nReset = '0') then`
319			`cmd_stop <= '0';`
320			`ial <= '0';`
321			`elsif (clk'event and clk = '1') then`
322			`if (rst = '1') then`
323			`cmd_stop <= '0';`
324			`ial <= '0';`
325			`else`
326	48	rherveille	`if (clk_en = '1') then`
327	52	rherveille	`if (cmd = I2C_CMD_STOP) then`
328	48	rherveille	`cmd_stop <= '1';`
329			`else`
330			`cmd_stop <= '0';`
331	52	rherveille	`end if;`
332	39	rherveille	`end if;`
333	31	rherveille
334	52	rherveille	`if (c_state = idle) then`
335	53	rherveille	`ial <= (sda_chk and not sSDA and isda_oen);`
336	52	rherveille	`else`
337	53	rherveille	`ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);`
338	52	rherveille	`end if;`
339
340	35	rherveille	`end if;`
341	31	rherveille	`end if;`
342			`end process gen_al;`
343	35	rherveille	`al <= ial;`
344	34	rherveille
345	31	rherveille	`-- generate dout signal, store dout on rising edge of SCL`
346			`gen_dout: process(clk)`
347			`begin`
348			`if (clk'event and clk = '1') then`
349			`if (sSCL = '1' and dSCL = '0') then`
350			`dout <= sSDA;`
351			`end if;`
352			`end if;`
353			`end process gen_dout;`
354	15	rherveille	`end block bus_status_ctrl;`
355
356
357			`-- generate statemachine`
358			`nxt_state_decoder : process (clk, nReset, c_state, cmd)`
359			`begin`
360	27	rherveille	`if (nReset = '0') then`
361			`c_state <= idle;`
362			`cmd_ack <= '0';`
363			`iscl_oen <= '1';`
364			`isda_oen <= '1';`
365	31	rherveille	`sda_chk <= '0';`
366	27	rherveille	`elsif (clk'event and clk = '1') then`
367	34	rherveille	`if (rst = '1' or ial = '1') then`
368	27	rherveille	`c_state <= idle;`
369			`cmd_ack <= '0';`
370			`iscl_oen <= '1';`
371			`isda_oen <= '1';`
372	31	rherveille	`sda_chk <= '0';`
373	27	rherveille	`else`
374			`cmd_ack <= '0'; -- default no acknowledge`
375	15	rherveille
376	27	rherveille	`if (clk_en = '1') then`
377			`case (c_state) is`
378			`-- idle`
379			`when idle =>`
380			`case cmd is`
381			`when I2C_CMD_START => c_state <= start_a;`
382			`when I2C_CMD_STOP => c_state <= stop_a;`
383			`when I2C_CMD_WRITE => c_state <= wr_a;`
384			`when I2C_CMD_READ => c_state <= rd_a;`
385			`when others => c_state <= idle; -- NOP command`
386			`end case;`
387	15	rherveille
388	27	rherveille	`iscl_oen <= iscl_oen; -- keep SCL in same state`
389			`isda_oen <= isda_oen; -- keep SDA in same state`
390	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
391	15	rherveille
392	27	rherveille	`-- start`
393			`when start_a =>`
394			`c_state <= start_b;`
395			`iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)`
396			`isda_oen <= '1'; -- set SDA high`
397	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
398	15	rherveille
399	27	rherveille	`when start_b =>`
400			`c_state <= start_c;`
401			`iscl_oen <= '1'; -- set SCL high`
402			`isda_oen <= '1'; -- keep SDA high`
403	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
404	15	rherveille
405	27	rherveille	`when start_c =>`
406			`c_state <= start_d;`
407			`iscl_oen <= '1'; -- keep SCL high`
408			`isda_oen <= '0'; -- set SDA low`
409	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
410	15	rherveille
411	27	rherveille	`when start_d =>`
412			`c_state <= start_e;`
413			`iscl_oen <= '1'; -- keep SCL high`
414			`isda_oen <= '0'; -- keep SDA low`
415	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
416	15	rherveille
417	27	rherveille	`when start_e =>`
418			`c_state <= idle;`
419			`cmd_ack <= '1'; -- command completed`
420			`iscl_oen <= '0'; -- set SCL low`
421			`isda_oen <= '0'; -- keep SDA low`
422	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
423	15	rherveille
424	27	rherveille	`-- stop`
425			`when stop_a =>`
426			`c_state <= stop_b;`
427	31	rherveille	`iscl_oen <= '0'; -- keep SCL low`
428	27	rherveille	`isda_oen <= '0'; -- set SDA low`
429	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
430	15	rherveille
431	27	rherveille	`when stop_b =>`
432			`c_state <= stop_c;`
433			`iscl_oen <= '1'; -- set SCL high`
434			`isda_oen <= '0'; -- keep SDA low`
435	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
436	15	rherveille
437	27	rherveille	`when stop_c =>`
438			`c_state <= stop_d;`
439			`iscl_oen <= '1'; -- keep SCL high`
440			`isda_oen <= '0'; -- keep SDA low`
441	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
442	15	rherveille
443	27	rherveille	`when stop_d =>`
444			`c_state <= idle;`
445			`cmd_ack <= '1'; -- command completed`
446			`iscl_oen <= '1'; -- keep SCL high`
447			`isda_oen <= '1'; -- set SDA high`
448	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
449	15	rherveille
450	27	rherveille	`-- read`
451			`when rd_a =>`
452			`c_state <= rd_b;`
453			`iscl_oen <= '0'; -- keep SCL low`
454			`isda_oen <= '1'; -- tri-state SDA`
455	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
456	15	rherveille
457	27	rherveille	`when rd_b =>`
458			`c_state <= rd_c;`
459			`iscl_oen <= '1'; -- set SCL high`
460			`isda_oen <= '1'; -- tri-state SDA`
461	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
462	15	rherveille
463	27	rherveille	`when rd_c =>`
464			`c_state <= rd_d;`
465			`iscl_oen <= '1'; -- keep SCL high`
466			`isda_oen <= '1'; -- tri-state SDA`
467	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
468	15	rherveille
469	27	rherveille	`when rd_d =>`
470			`c_state <= idle;`
471			`cmd_ack <= '1'; -- command completed`
472			`iscl_oen <= '0'; -- set SCL low`
473			`isda_oen <= '1'; -- tri-state SDA`
474	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
475	15	rherveille
476	27	rherveille	`-- write`
477			`when wr_a =>`
478			`c_state <= wr_b;`
479			`iscl_oen <= '0'; -- keep SCL low`
480			`isda_oen <= din; -- set SDA`
481	31	rherveille	`sda_chk <= '0'; -- don't check SDA (SCL low)`
482	15	rherveille
483	27	rherveille	`when wr_b =>`
484			`c_state <= wr_c;`
485			`iscl_oen <= '1'; -- set SCL high`
486			`isda_oen <= din; -- keep SDA`
487	31	rherveille	`sda_chk <= '1'; -- check SDA`
488	15	rherveille
489	27	rherveille	`when wr_c =>`
490			`c_state <= wr_d;`
491			`iscl_oen <= '1'; -- keep SCL high`
492			`isda_oen <= din; -- keep SDA`
493	31	rherveille	`sda_chk <= '1'; -- check SDA`
494	15	rherveille
495	27	rherveille	`when wr_d =>`
496			`c_state <= idle;`
497			`cmd_ack <= '1'; -- command completed`
498			`iscl_oen <= '0'; -- set SCL low`
499			`isda_oen <= din; -- keep SDA`
500	31	rherveille	`sda_chk <= '0'; -- don't check SDA (SCL low)`

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