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[/] [keras_to_fpga/] [trunk/] [sim/] [tests/] [tb_xor/] [tb_top.sv] - Blame information for rev 3

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1 2 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module tb_top;
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  import uvm_pkg::*;
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  `include "uvm_macros.svh"
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  import tb_top_pkg::*;
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  // --------------------------------------------------------------------
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  localparam realtime PERIODS[1] = '{10ns};
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  localparam CLOCK_COUNT = $size(PERIODS);
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  // --------------------------------------------------------------------
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  bit tb_clk[CLOCK_COUNT];
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  wire tb_aresetn;
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  bit tb_reset[CLOCK_COUNT];
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  tb_base #(.N(CLOCK_COUNT), .PERIODS(PERIODS)) tb(.*);
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  // --------------------------------------------------------------------
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  wire aclk = tb_clk[0];
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  wire aresetn = ~tb_reset[0];
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  // --------------------------------------------------------------------
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  axis_if #(.N(N), .U(U)) axis_in(.*);
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  axis_if #(.N(N), .U(U)) axis_out(.*);
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  axis_if #(.N(N), .U(U)) axis_stub(.*);
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  // --------------------------------------------------------------------
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  xor_top #(.N(N), .DIR(DIR)) dut(.*);
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  // // --------------------------------------------------------------------
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  // bind dut axis_checker #(.N(N), .U(U)) dut_b(.*);
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  // --------------------------------------------------------------------
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  // tb_dut_config #(N, U) cfg_h = new(axis_in, axis_out);
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  tb_dut_config #(N, U) cfg_h = new(axis_in, axis_stub);
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  assign axis_out.tready = 1;
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  initial
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  begin
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    cfg_h.init( .pixels_per_line(AW)
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              , .lines_per_frame(AH)
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              , .bits_per_pixel(B * 8)
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              );
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    uvm_config_db #(tb_dut_config #(N, U))::set(null, "*", "tb_dut_config", cfg_h);
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    run_test("t_debug");
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    // repeat(16) @(posedge aclk);
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    // $stop;
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  end
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  // --------------------------------------------------------------------
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  int in_index = 0;
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  real in_data;
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  initial
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    fork
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      forever @(negedge aclk)
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        if(axis_in.tvalid & axis_in.tready)
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        begin
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          in_data = $bitstoshortreal(axis_in.tdata);
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          $display("%s", {20{"-"}});
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          $display("%d | binary   |input = %h", in_index, axis_in.tdata);
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          $display("%d | IEEE 754 |input = %9.7F", in_index, in_data);
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          if(axis_in.tlast)
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          begin
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            $display("%s", {20{"+"}});
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            in_index++;
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          end
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        end
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    join_none
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  // --------------------------------------------------------------------
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  int out_index = 0;
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  real out_data;
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  initial
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    fork
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      forever @(negedge aclk)
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        if(axis_out.tvalid & axis_out.tready)
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        begin
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          out_data = $bitstoshortreal(axis_out.tdata);
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          $display("%s", {20{"-"}});
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          $display("%d | binary   |result = %h", out_index, axis_out.tdata);
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          $display("%d | IEEE 754 |result = %9.7F", out_index, out_data);
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          out_index++;
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        end
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    join_none
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// --------------------------------------------------------------------
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endmodule

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