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[/] [keras_to_fpga/] [trunk/] [src/] [math/] [axis_mac.sv] - Blame information for rev 2

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1 2 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axis_mac #(W=32)
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  (
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    axis_if axis_ay,
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    axis_if axis_az,
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    output [31:0] result,
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    output valid,
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    input   aclk,
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    input   aresetn
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  );
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  // --------------------------------------------------------------------
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  wire both_valid = axis_ay.tvalid & axis_az.tvalid;
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  wire tlast_in = both_valid & axis_ay.tlast & axis_az.tlast;
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  // --------------------------------------------------------------------
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  enum reg [3:0]
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    {
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      IDLE        = 4'b0001,
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      ACCUMULATE  = 4'b0010,
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      FLUSH       = 4'b0100,
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      READY       = 4'b1000
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    } state, next_state;
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  // --------------------------------------------------------------------
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  always_ff @(posedge aclk)
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    if(~aresetn)
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      state <= IDLE;
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    else
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      state <= next_state;
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  // --------------------------------------------------------------------
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  always_comb
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    case(state)
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      IDLE:       if(both_valid)
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                    next_state <= ACCUMULATE;
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                  else
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                    next_state <= IDLE;
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      ACCUMULATE: if(tlast_in)
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                    next_state <= FLUSH;
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                  else
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                    next_state <= ACCUMULATE;
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      FLUSH:      next_state <= READY;
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      READY:      if(both_valid)
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                    next_state <= ACCUMULATE;
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                  else
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                    next_state <= IDLE;
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      default:    next_state <= IDLE;
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    endcase
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  // --------------------------------------------------------------------
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  wire accumulate = ((state == ACCUMULATE) & both_valid);
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  wire ena = aresetn & (accumulate | (state == FLUSH));
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  wire [W-1:0] ay = axis_ay.tdata[W-1:0];
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  wire [W-1:0] az = axis_az.tdata[W-1:0];
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  wire [1:0] aclr = {~aresetn, ~aresetn | valid};
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  mac mac(.clk(aclk), .*);
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  // --------------------------------------------------------------------
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  assign axis_ay.tready = accumulate;
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  assign axis_az.tready = accumulate;
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  assign valid = (state == READY);
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// --------------------------------------------------------------------
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endmodule

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