Subversion Repositories keras_to_fpga

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//////////////////////////////////////////////////////////////////////

module

  axis_dense_neuron

  #(

    int N,

    int A,

    string FILE_NAME,

    int START,

    int STOP,

    string ACTIVATION

  )

  (

    axis_if axis_in,

    axis_if axis_out,

    output error,

    input   aclk,

    input   aresetn

  );

  // --------------------------------------------------------------------

  axis_if #(4) axis_bias(.*);

  assign axis_bias.tdata = $shortrealtobits(1.0);

  assign axis_bias.tvalid = 1;

  assign axis_bias.tlast = 1;

  // --------------------------------------------------------------------

  axis_if #(4) axis_az(.*);

  axis_if #(4) axis_cat[2](.*);

  axis_alias axis_alias_bias(axis_bias, axis_cat[0]);

  axis_alias axis_alias_in(axis_in, axis_cat[1]);

  axis_catenate #(N)

    axis_catenate_i(.axis_in(axis_cat), .axis_out(axis_az), .*);

  // --------------------------------------------------------------------

  axis_if #(.N(N)) axis_rom(.*);

  axis_rom #(N, A, FILE_NAME, START, STOP)

    axis_rom_i(.axis_out(axis_rom), .*);

  // --------------------------------------------------------------------

  wire [31:0] result;

  wire valid;

  axis_mac axis_mac_i(.axis_ay(axis_rom), .*);

  // --------------------------------------------------------------------

  // ReLU activation function

  // wire [31:0] activation = result[31] ? 0 : result;

  wire [31:0] activation;

  generate

  begin: activation_gen

    if(ACTIVATION == "ReLU")

      relu relu_i(.*);

    else if(ACTIVATION == "Linear")

      linear linear_i(.*);

    else

      initial $stop;

  end

  endgenerate

  // --------------------------------------------------------------------

  wire wr_full;

  wire [(N*8)-1:0] wr_data = activation;

  wire wr_en = valid;

  wire rd_empty;

  wire [(N*8)-1:0] rd_data;

  wire rd_en = axis_out.tvalid & axis_out.tready;

  // tiny_sync_fifo #(N*8) fifo_i(.clk(aclk), .reset(~aresetn), .*);

  wire  [$clog2(64):0] count; // fixme

  sync_fifo #(N*8, 64) fifo_i(.clk(aclk), .reset(~aresetn), .*);  // fix me

  // --------------------------------------------------------------------

  assign axis_out.tvalid = ~rd_empty;

  assign axis_out.tdata = rd_data;

  assign axis_out.tlast = 1;

  assign error = wr_full & valid;

// --------------------------------------------------------------------

endmodule