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kavi |
-- File automatically generated by "cdfg2hdl".
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-- Filename: cordic.vhd
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-- Date: 27 November 2010 08:42:54 PM
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-- Author: Nikolaos Kavvadias (C) 2009, 2010
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library IEEE;
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use WORK.operpack.all;
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use WORK.cordic_cdt_pkg.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity cordic is
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port (
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clk : in std_logic;
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reset : in std_logic;
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start : in std_logic;
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direction : in std_logic_vector(15 downto 0);
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mode : in std_logic_vector(15 downto 0);
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xin : in std_logic_vector(15 downto 0);
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yin : in std_logic_vector(15 downto 0);
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zin : in std_logic_vector(15 downto 0);
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xout : out std_logic_vector(15 downto 0);
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yout : out std_logic_vector(15 downto 0);
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zout : out std_logic_vector(15 downto 0);
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done : out std_logic;
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ready : out std_logic
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);
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end cordic;
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architecture fsmd of cordic is
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type state_type is (S_ENTRY, S_EXIT, S_001_001, S_002_001, S_003_001, S_004_001);
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signal current_state, next_state: state_type;
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signal cordic_hyp_steps : cordic_hyp_steps_type := (
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14 => "0000000000001101",
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13 => "0000000000001101",
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12 => "0000000000001100",
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11 => "0000000000001011",
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10 => "0000000000001010",
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9 => "0000000000001001",
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8 => "0000000000001000",
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7 => "0000000000000111",
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6 => "0000000000000110",
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5 => "0000000000000101",
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4 => "0000000000000100",
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3 => "0000000000000100",
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2 => "0000000000000011",
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1 => "0000000000000010",
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others => (others => '0'));
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signal cordic_tab : cordic_tab_type := (
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41 => "0000000000000001",
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40 => "0000000000000011",
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39 => "0000000000000111",
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38 => "0000000000001111",
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37 => "0000000000011111",
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36 => "0000000000111111",
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35 => "0000000001111111",
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34 => "0000000011111111",
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33 => "0000000111111111",
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32 => "0000001111111110",
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31 => "0000011111110101",
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30 => "0000111110101101",
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29 => "0001110110101100",
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28 => "0011001001000011",
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27 => "0000000000000010",
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26 => "0000000000000100",
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25 => "0000000000001000",
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24 => "0000000000010000",
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23 => "0000000000100000",
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22 => "0000000001000000",
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21 => "0000000010000000",
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20 => "0000000100000000",
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19 => "0000001000000000",
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18 => "0000010000000000",
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17 => "0000100000000000",
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16 => "0001000000000000",
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15 => "0010000000000000",
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14 => "0100000000000000",
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13 => "0000000000000010",
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12 => "0000000000000100",
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11 => "0000000000001000",
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10 => "0000000000010000",
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9 => "0000000000100000",
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8 => "0000000001000000",
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7 => "0000000010000000",
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6 => "0000000100000000",
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5 => "0000001000000000",
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4 => "0000010000000001",
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3 => "0000100000001010",
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2 => "0001000001011000",
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1 => "0010001100100111",
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others => (others => '0'));
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signal t5_next : std_logic_vector(15 downto 0);
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signal t5_reg : std_logic_vector(15 downto 0);
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signal x2_next : std_logic_vector(15 downto 0);
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signal x2_reg : std_logic_vector(15 downto 0);
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signal y1_next : std_logic_vector(15 downto 0);
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signal y1_reg : std_logic_vector(15 downto 0);
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signal z2_next : std_logic_vector(15 downto 0);
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signal z2_reg : std_logic_vector(15 downto 0);
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signal k_next : std_logic_vector(15 downto 0);
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signal k_reg : std_logic_vector(15 downto 0);
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signal zero_next : std_logic_vector(15 downto 0);
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signal zero_reg : std_logic_vector(15 downto 0);
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signal one_next : std_logic_vector(15 downto 0);
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signal one_reg : std_logic_vector(15 downto 0);
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signal t1_next : std_logic_vector(15 downto 0);
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signal t1_reg : std_logic_vector(15 downto 0);
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signal tabval_next : std_logic_vector(15 downto 0);
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signal tabval_reg : std_logic_vector(15 downto 0);
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signal x_next : std_logic_vector(15 downto 0);
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signal x_reg : std_logic_vector(15 downto 0);
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signal y_next : std_logic_vector(15 downto 0);
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signal y_reg : std_logic_vector(15 downto 0);
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signal z_next : std_logic_vector(15 downto 0);
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signal z_reg : std_logic_vector(15 downto 0);
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signal ldirection_next : std_logic_vector(15 downto 0);
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signal ldirection_reg : std_logic_vector(15 downto 0);
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signal lmode_next : std_logic_vector(15 downto 0);
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signal lmode_reg : std_logic_vector(15 downto 0);
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signal t4_next : std_logic_vector(15 downto 0);
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signal t4_reg : std_logic_vector(15 downto 0);
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signal ybyk_next : std_logic_vector(15 downto 0);
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signal ybyk_reg : std_logic_vector(15 downto 0);
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signal t7_next : std_logic_vector(15 downto 0);
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signal t7_reg : std_logic_vector(15 downto 0);
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signal d_next : std_logic_vector(15 downto 0);
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signal d_reg : std_logic_vector(15 downto 0);
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signal t0_next : std_logic_vector(15 downto 0);
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signal t0_reg : std_logic_vector(15 downto 0);
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signal offset_next : std_logic_vector(15 downto 0);
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signal offset_reg : std_logic_vector(15 downto 0);
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signal kfinal_next : std_logic_vector(15 downto 0);
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signal kfinal_reg : std_logic_vector(15 downto 0);
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signal kk_next : std_logic_vector(15 downto 0);
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signal kk_reg : std_logic_vector(15 downto 0);
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signal t9_next : std_logic_vector(15 downto 0);
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signal t9_reg : std_logic_vector(15 downto 0);
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signal t3_next : std_logic_vector(15 downto 0);
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signal t3_reg : std_logic_vector(15 downto 0);
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signal t2_next : std_logic_vector(15 downto 0);
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signal t2_reg : std_logic_vector(15 downto 0);
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signal xbyk_next : std_logic_vector(15 downto 0);
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signal xbyk_reg : std_logic_vector(15 downto 0);
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signal t6_next : std_logic_vector(15 downto 0);
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signal t6_reg : std_logic_vector(15 downto 0);
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signal t8_next : std_logic_vector(15 downto 0);
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signal t8_reg : std_logic_vector(15 downto 0);
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signal x1_next : std_logic_vector(15 downto 0);
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signal x1_reg : std_logic_vector(15 downto 0);
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signal y2_next : std_logic_vector(15 downto 0);
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signal y2_reg : std_logic_vector(15 downto 0);
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signal z1_next : std_logic_vector(15 downto 0);
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signal z1_reg : std_logic_vector(15 downto 0);
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signal zout_next : std_logic_vector(15 downto 0);
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signal zout_reg : std_logic_vector(15 downto 0);
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signal yout_next : std_logic_vector(15 downto 0);
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signal yout_reg : std_logic_vector(15 downto 0);
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signal xout_next : std_logic_vector(15 downto 0);
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signal xout_reg : std_logic_vector(15 downto 0);
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constant CNST_28 : std_logic_vector(15 downto 0) := "0000000000011100";
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constant CNST_2 : std_logic_vector(15 downto 0) := "0000000000000010";
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constant CNST_15 : std_logic_vector(15 downto 0) := "0000000000001111";
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constant CNST_14 : std_logic_vector(15 downto 0) := "0000000000001110";
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constant CNST_1 : std_logic_vector(15 downto 0) := "0000000000000001";
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constant CNST_0 : std_logic_vector(15 downto 0) := "0000000000000000";
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begin
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-- current state logic
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process (clk, reset)
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begin
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if (reset = '1') then
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current_state <= S_ENTRY;
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t5_reg <= (others => '0');
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x2_reg <= (others => '0');
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y1_reg <= (others => '0');
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z2_reg <= (others => '0');
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k_reg <= (others => '0');
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zero_reg <= (others => '0');
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one_reg <= (others => '0');
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t1_reg <= (others => '0');
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tabval_reg <= (others => '0');
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x_reg <= (others => '0');
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y_reg <= (others => '0');
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z_reg <= (others => '0');
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ldirection_reg <= (others => '0');
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lmode_reg <= (others => '0');
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t4_reg <= (others => '0');
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ybyk_reg <= (others => '0');
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t7_reg <= (others => '0');
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d_reg <= (others => '0');
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t0_reg <= (others => '0');
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offset_reg <= (others => '0');
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kfinal_reg <= (others => '0');
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kk_reg <= (others => '0');
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t9_reg <= (others => '0');
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t3_reg <= (others => '0');
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t2_reg <= (others => '0');
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xbyk_reg <= (others => '0');
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t6_reg <= (others => '0');
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t8_reg <= (others => '0');
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x1_reg <= (others => '0');
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y2_reg <= (others => '0');
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z1_reg <= (others => '0');
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zout_reg <= (others => '0');
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yout_reg <= (others => '0');
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xout_reg <= (others => '0');
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elsif (clk = '1' and clk'EVENT) then
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current_state <= next_state;
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t5_reg <= t5_next;
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x2_reg <= x2_next;
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y1_reg <= y1_next;
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z2_reg <= z2_next;
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k_reg <= k_next;
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zero_reg <= zero_next;
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one_reg <= one_next;
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t1_reg <= t1_next;
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tabval_reg <= tabval_next;
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x_reg <= x_next;
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y_reg <= y_next;
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z_reg <= z_next;
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ldirection_reg <= ldirection_next;
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lmode_reg <= lmode_next;
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t4_reg <= t4_next;
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ybyk_reg <= ybyk_next;
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t7_reg <= t7_next;
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d_reg <= d_next;
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t0_reg <= t0_next;
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offset_reg <= offset_next;
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kfinal_reg <= kfinal_next;
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kk_reg <= kk_next;
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t9_reg <= t9_next;
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t3_reg <= t3_next;
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t2_reg <= t2_next;
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xbyk_reg <= xbyk_next;
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t6_reg <= t6_next;
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t8_reg <= t8_next;
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x1_reg <= x1_next;
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y2_reg <= y2_next;
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z1_reg <= z1_next;
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zout_reg <= zout_next;
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yout_reg <= yout_next;
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xout_reg <= xout_next;
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end if;
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end process;
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| 248 |
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-- next state and output logic
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| 249 |
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process (current_state, start,
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direction,
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mode,
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| 252 |
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xin,
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yin,
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| 254 |
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zin,
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xout_reg,
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yout_reg,
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zout_reg,
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| 258 |
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t5_reg, t5_next,
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| 259 |
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x2_reg, x2_next,
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| 260 |
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y1_reg, y1_next,
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| 261 |
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z2_reg, z2_next,
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| 262 |
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k_reg, k_next,
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| 263 |
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zero_reg, zero_next,
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| 264 |
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one_reg, one_next,
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| 265 |
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t1_reg, t1_next,
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| 266 |
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tabval_reg, tabval_next,
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| 267 |
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x_reg, x_next,
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| 268 |
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y_reg, y_next,
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| 269 |
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z_reg, z_next,
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| 270 |
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ldirection_reg, ldirection_next,
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| 271 |
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lmode_reg, lmode_next,
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| 272 |
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t4_reg, t4_next,
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| 273 |
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ybyk_reg, ybyk_next,
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| 274 |
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t7_reg, t7_next,
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| 275 |
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d_reg, d_next,
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| 276 |
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t0_reg, t0_next,
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| 277 |
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offset_reg, offset_next,
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| 278 |
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kfinal_reg, kfinal_next,
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| 279 |
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kk_reg, kk_next,
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| 280 |
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t9_reg, t9_next,
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| 281 |
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t3_reg, t3_next,
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| 282 |
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t2_reg, t2_next,
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| 283 |
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xbyk_reg, xbyk_next,
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| 284 |
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t6_reg, t6_next,
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| 285 |
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t8_reg, t8_next,
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| 286 |
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x1_reg, x1_next,
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| 287 |
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y2_reg, y2_next,
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| 288 |
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z1_reg, z1_next
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| 289 |
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)
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| 290 |
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begin
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| 291 |
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done <= '0';
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| 292 |
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ready <= '0';
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| 293 |
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t5_next <= t5_reg;
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| 294 |
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x2_next <= x2_reg;
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| 295 |
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y1_next <= y1_reg;
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| 296 |
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z2_next <= z2_reg;
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| 297 |
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k_next <= k_reg;
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| 298 |
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zero_next <= zero_reg;
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| 299 |
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one_next <= one_reg;
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| 300 |
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t1_next <= t1_reg;
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| 301 |
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tabval_next <= tabval_reg;
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| 302 |
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x_next <= x_reg;
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| 303 |
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y_next <= y_reg;
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| 304 |
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z_next <= z_reg;
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| 305 |
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ldirection_next <= ldirection_reg;
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| 306 |
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lmode_next <= lmode_reg;
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| 307 |
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t4_next <= t4_reg;
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| 308 |
|
|
ybyk_next <= ybyk_reg;
|
| 309 |
|
|
t7_next <= t7_reg;
|
| 310 |
|
|
d_next <= d_reg;
|
| 311 |
|
|
t0_next <= t0_reg;
|
| 312 |
|
|
offset_next <= offset_reg;
|
| 313 |
|
|
kfinal_next <= kfinal_reg;
|
| 314 |
|
|
kk_next <= kk_reg;
|
| 315 |
|
|
t9_next <= t9_reg;
|
| 316 |
|
|
t3_next <= t3_reg;
|
| 317 |
|
|
t2_next <= t2_reg;
|
| 318 |
|
|
xbyk_next <= xbyk_reg;
|
| 319 |
|
|
t6_next <= t6_reg;
|
| 320 |
|
|
t8_next <= t8_reg;
|
| 321 |
|
|
x1_next <= x1_reg;
|
| 322 |
|
|
y2_next <= y2_reg;
|
| 323 |
|
|
z1_next <= z1_reg;
|
| 324 |
|
|
zout_next <= zout_reg;
|
| 325 |
|
|
yout_next <= yout_reg;
|
| 326 |
|
|
xout_next <= xout_reg;
|
| 327 |
|
|
case current_state is
|
| 328 |
|
|
when S_ENTRY =>
|
| 329 |
|
|
ready <= '1';
|
| 330 |
|
|
if (start = '1') then
|
| 331 |
|
|
next_state <= S_001_001;
|
| 332 |
|
|
else
|
| 333 |
|
|
next_state <= S_ENTRY;
|
| 334 |
|
|
end if;
|
| 335 |
|
|
when S_001_001 =>
|
| 336 |
|
|
zero_next <= CNST_0(15 downto 0);
|
| 337 |
|
|
one_next <= CNST_1(15 downto 0);
|
| 338 |
|
|
x_next <= xin(15 downto 0);
|
| 339 |
|
|
y_next <= yin(15 downto 0);
|
| 340 |
|
|
z_next <= zin(15 downto 0);
|
| 341 |
|
|
ldirection_next <= direction(15 downto 0);
|
| 342 |
|
|
lmode_next <= mode(15 downto 0);
|
| 343 |
|
|
k_next <= CNST_0(15 downto 0);
|
| 344 |
|
|
if (lmode_next = CNST_1(15 downto 0)) then
|
| 345 |
|
|
t0_next <= CNST_14(15 downto 0);
|
| 346 |
|
|
else
|
| 347 |
|
|
t0_next <= CNST_28(15 downto 0);
|
| 348 |
|
|
end if;
|
| 349 |
|
|
if (lmode_next = CNST_2(15 downto 0)) then
|
| 350 |
|
|
offset_next <= CNST_0(15 downto 0);
|
| 351 |
|
|
else
|
| 352 |
|
|
offset_next <= t0_next(15 downto 0);
|
| 353 |
|
|
end if;
|
| 354 |
|
|
if (lmode_next = CNST_2(15 downto 0)) then
|
| 355 |
|
|
kfinal_next <= CNST_15(15 downto 0);
|
| 356 |
|
|
else
|
| 357 |
|
|
kfinal_next <= CNST_14(15 downto 0);
|
| 358 |
|
|
end if;
|
| 359 |
|
|
next_state <= S_002_001;
|
| 360 |
|
|
when S_002_001 =>
|
| 361 |
|
|
if (k_reg < kfinal_reg(15 downto 0)) then
|
| 362 |
|
|
next_state <= S_003_001;
|
| 363 |
|
|
else
|
| 364 |
|
|
next_state <= S_004_001;
|
| 365 |
|
|
end if;
|
| 366 |
|
|
when S_003_001 =>
|
| 367 |
|
|
t1_next <= cordic_hyp_steps(to_integer(unsigned(k_reg(3 downto 0))));
|
| 368 |
|
|
if (lmode_reg /= CNST_2(15 downto 0)) then
|
| 369 |
|
|
kk_next <= k_reg(15 downto 0);
|
| 370 |
|
|
else
|
| 371 |
|
|
kk_next <= t1_next(15 downto 0);
|
| 372 |
|
|
end if;
|
| 373 |
|
|
t2_next <= shrv4(y_reg, kk_next, '1');
|
| 374 |
|
|
t3_next <= std_logic_vector(not(unsigned(t2_next(15 downto 0))) + unsigned(ONE));
|
| 375 |
|
|
xbyk_next <= shrv4(x_reg, kk_next, '1');
|
| 376 |
|
|
if (lmode_reg = CNST_1(15 downto 0)) then
|
| 377 |
|
|
t4_next <= zero_reg(15 downto 0);
|
| 378 |
|
|
else
|
| 379 |
|
|
t4_next <= t2_next(15 downto 0);
|
| 380 |
|
|
end if;
|
| 381 |
|
|
if (lmode_reg = CNST_2(15 downto 0)) then
|
| 382 |
|
|
ybyk_next <= t3_next(15 downto 0);
|
| 383 |
|
|
else
|
| 384 |
|
|
ybyk_next <= t4_next(15 downto 0);
|
| 385 |
|
|
end if;
|
| 386 |
|
|
t5_next <= std_logic_vector(signed(kk_next) + signed(offset_reg(15 downto 0)));
|
| 387 |
|
|
tabval_next <= cordic_tab(to_integer(unsigned(t5_next(5 downto 0))));
|
| 388 |
|
|
t6_next(15 downto 1) <= (others => z_reg(15));
|
| 389 |
|
|
t6_next(0 downto 0) <= z_reg(15 downto 15);
|
| 390 |
|
|
if (t6_next = CNST_0(15 downto 0)) then
|
| 391 |
|
|
t7_next <= zero_reg(15 downto 0);
|
| 392 |
|
|
else
|
| 393 |
|
|
t7_next <= one_reg(15 downto 0);
|
| 394 |
|
|
end if;
|
| 395 |
|
|
t8_next(15 downto 1) <= (others => y_reg(15));
|
| 396 |
|
|
t8_next(0 downto 0) <= y_reg(15 downto 15);
|
| 397 |
|
|
if (t8_next /= CNST_0(15 downto 0)) then
|
| 398 |
|
|
t9_next <= zero_reg(15 downto 0);
|
| 399 |
|
|
else
|
| 400 |
|
|
t9_next <= one_reg(15 downto 0);
|
| 401 |
|
|
end if;
|
| 402 |
|
|
if (ldirection_reg = CNST_0(15 downto 0)) then
|
| 403 |
|
|
d_next <= t7_next(15 downto 0);
|
| 404 |
|
|
else
|
| 405 |
|
|
d_next <= t9_next(15 downto 0);
|
| 406 |
|
|
end if;
|
| 407 |
|
|
x1_next <= std_logic_vector(signed(x_reg) - signed(ybyk_next(15 downto 0)));
|
| 408 |
|
|
x2_next <= std_logic_vector(signed(x_reg) + signed(ybyk_next(15 downto 0)));
|
| 409 |
|
|
y1_next <= std_logic_vector(signed(y_reg) + signed(xbyk_next(15 downto 0)));
|
| 410 |
|
|
y2_next <= std_logic_vector(signed(y_reg) - signed(xbyk_next(15 downto 0)));
|
| 411 |
|
|
z1_next <= std_logic_vector(signed(z_reg) - signed(tabval_next(15 downto 0)));
|
| 412 |
|
|
z2_next <= std_logic_vector(signed(z_reg) + signed(tabval_next(15 downto 0)));
|
| 413 |
|
|
if (d_next = CNST_0(15 downto 0)) then
|
| 414 |
|
|
x_next <= x1_next(15 downto 0);
|
| 415 |
|
|
else
|
| 416 |
|
|
x_next <= x2_next(15 downto 0);
|
| 417 |
|
|
end if;
|
| 418 |
|
|
if (d_next = CNST_0(15 downto 0)) then
|
| 419 |
|
|
y_next <= y1_next(15 downto 0);
|
| 420 |
|
|
else
|
| 421 |
|
|
y_next <= y2_next(15 downto 0);
|
| 422 |
|
|
end if;
|
| 423 |
|
|
if (d_next = CNST_0(15 downto 0)) then
|
| 424 |
|
|
z_next <= z1_next(15 downto 0);
|
| 425 |
|
|
else
|
| 426 |
|
|
z_next <= z2_next(15 downto 0);
|
| 427 |
|
|
end if;
|
| 428 |
|
|
k_next <= std_logic_vector(signed(k_reg) + signed(CNST_1(15 downto 0)));
|
| 429 |
|
|
if (k_next < kfinal_reg(15 downto 0)) then
|
| 430 |
|
|
next_state <= S_003_001;
|
| 431 |
|
|
else
|
| 432 |
|
|
next_state <= S_004_001;
|
| 433 |
|
|
end if;
|
| 434 |
|
|
when S_004_001 =>
|
| 435 |
|
|
xout_next <= x_reg(15 downto 0);
|
| 436 |
|
|
yout_next <= y_reg(15 downto 0);
|
| 437 |
|
|
zout_next <= z_reg(15 downto 0);
|
| 438 |
|
|
next_state <= S_EXIT;
|
| 439 |
|
|
when S_EXIT =>
|
| 440 |
|
|
done <= '1';
|
| 441 |
|
|
next_state <= S_ENTRY;
|
| 442 |
|
|
end case;
|
| 443 |
|
|
end process;
|
| 444 |
|
|
|
| 445 |
|
|
zout <= zout_reg;
|
| 446 |
|
|
yout <= yout_reg;
|
| 447 |
|
|
xout <= xout_reg;
|
| 448 |
|
|
|
| 449 |
|
|
end fsmd;
|
