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[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [platform/] [ibus_adapter.vhd] - Blame information for rev 9

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1 9 ring0_mipt
---------------------------------------------------------------------
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-- IBUS adapter
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--
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-- Part of the LXP32 test platform
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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-- Converts the Low Latency Interface to WISHBONE registered
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-- feedback protocol.
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--
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-- Note: regardless of whether this description is synthesizable,
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-- it was designed exclusively for simulation purposes.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ibus_adapter is
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        port(
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                clk_i: in std_logic;
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                rst_i: in std_logic;
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                ibus_cyc_i: in std_logic;
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                ibus_stb_i: in std_logic;
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                ibus_cti_i: in std_logic_vector(2 downto 0);
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                ibus_bte_i: in std_logic_vector(1 downto 0);
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                ibus_ack_o: out std_logic;
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                ibus_adr_i: in std_logic_vector(29 downto 0);
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                ibus_dat_o: out std_logic_vector(31 downto 0);
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                lli_re_o: out std_logic;
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                lli_adr_o: out std_logic_vector(29 downto 0);
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                lli_dat_i: in std_logic_vector(31 downto 0);
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                lli_busy_i: in std_logic
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        );
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end entity;
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architecture rtl of ibus_adapter is
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constant burst_delay: integer:=5;
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signal burst_delay_cnt: integer:=0;
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signal delay_burst: std_logic;
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signal re: std_logic;
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signal requested: std_logic:='0';
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signal adr: unsigned(29 downto 0);
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signal ack: std_logic;
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begin
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-- Insert burst delay
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process (clk_i) is
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begin
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        if rising_edge(clk_i) then
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                if rst_i='1' then
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                        burst_delay_cnt<=0;
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                elsif ibus_cyc_i='0' then
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                        burst_delay_cnt<=burst_delay;
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                elsif burst_delay_cnt/=0 then
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                        burst_delay_cnt<=burst_delay_cnt-1;
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                end if;
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        end if;
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end process;
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delay_burst<='1' when burst_delay_cnt/=0 else '0';
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-- Generate ACK signal
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process (clk_i) is
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begin
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        if rising_edge(clk_i) then
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                if rst_i='1' then
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                        requested<='0';
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                elsif lli_busy_i='0' then
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                        requested<=re;
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                end if;
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        end if;
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end process;
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ack<=requested and not lli_busy_i;
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-- Generate LLI signals
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re<=(ibus_cyc_i and ibus_stb_i and not delay_burst) when ack='0' or
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        (ibus_cti_i="010" and ibus_bte_i="00") else '0';
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adr<=unsigned(ibus_adr_i) when re='1' and ack='0' else
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        unsigned(ibus_adr_i)+1 when re='1' and ack='1' else
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        (others=>'-');
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lli_re_o<=re;
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lli_adr_o<=std_logic_vector(adr);
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-- Generate IBUS signals
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ibus_ack_o<=ack;
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ibus_dat_o<=lli_dat_i when ack='1' else (others=>'-');
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end architecture;

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