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Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [platform/] [platform.vhd] - Blame information for rev 9

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---------------------------------------------------------------------
-- LXP32 platform top-level design unit
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- A SoC-like simulation platform for the LXP32 CPU, containing
-- a few peripherals such as program RAM, timer and coprocessor.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity platform is
        generic(
                CPU_DBUS_RMW: boolean;
                CPU_MUL_ARCH: string;
                MODEL_LXP32C: boolean;
                THROTTLE_DBUS: boolean;
                THROTTLE_IBUS: boolean
        );
        port(
                clk_i: in std_logic;
                rst_i: in std_logic;
                cpu_rst_i: in std_logic;
 
                wbm_cyc_o: out std_logic;
                wbm_stb_o: out std_logic;
                wbm_we_o: out std_logic;
                wbm_sel_o: out std_logic_vector(3 downto 0);
                wbm_ack_i: in std_logic;
                wbm_adr_o: out std_logic_vector(27 downto 2);
                wbm_dat_o: out std_logic_vector(31 downto 0);
                wbm_dat_i: in std_logic_vector(31 downto 0);
 
                wbs_cyc_i: in std_logic;
                wbs_stb_i: in std_logic;
                wbs_we_i: in std_logic;
                wbs_sel_i: in std_logic_vector(3 downto 0);
                wbs_ack_o: out std_logic;
                wbs_adr_i: in std_logic_vector(31 downto 2);
                wbs_dat_i: in std_logic_vector(31 downto 0);
                wbs_dat_o: out std_logic_vector(31 downto 0);
 
                gp_io: inout std_logic_vector(31 downto 0)
        );
end entity;
 
architecture rtl of platform is
 
type wbm_type is record
        cyc: std_logic;
        stb: std_logic;
        we: std_logic;
        sel: std_logic_vector(3 downto 0);
        ack: std_logic;
        adr: std_logic_vector(31 downto 2);
        wdata: std_logic_vector(31 downto 0);
        rdata: std_logic_vector(31 downto 0);
end record;
 
type wbs_type is record
        cyc: std_logic;
        stb: std_logic;
        we: std_logic;
        sel: std_logic_vector(3 downto 0);
        ack: std_logic;
        adr: std_logic_vector(27 downto 2);
        wdata: std_logic_vector(31 downto 0);
        rdata: std_logic_vector(31 downto 0);
end record;
 
type ibus_type is record
        cyc: std_logic;
        stb: std_logic;
        cti: std_logic_vector(2 downto 0);
        bte: std_logic_vector(1 downto 0);
        ack: std_logic;
        adr: std_logic_vector(29 downto 0);
        dat: std_logic_vector(31 downto 0);
end record;
 
signal cpu_rst: std_logic;
signal cpu_irq: std_logic_vector(7 downto 0);
signal cpu_dbus: wbm_type;
signal cpu_ibus: ibus_type;
 
signal lli_re: std_logic;
signal lli_adr: std_logic_vector(29 downto 0);
signal lli_dat: std_logic_vector(31 downto 0);
signal lli_busy: std_logic;
 
signal monitor_dbus: wbm_type;
 
signal ram_wb: wbs_type;
 
signal timer_wb: wbs_type;
signal timer_elapsed: std_logic;
 
signal coprocessor_wb: wbs_type;
signal coprocessor_irq: std_logic;
 
begin
 
-- Interconnect
 
intercon_inst: entity work.intercon(rtl)
        port map(
                clk_i=>clk_i,
                rst_i=>rst_i,
 
                s0_cyc_i=>wbs_cyc_i,
                s0_stb_i=>wbs_stb_i,
                s0_we_i=>wbs_we_i,
                s0_sel_i=>wbs_sel_i,
                s0_ack_o=>wbs_ack_o,
                s0_adr_i=>wbs_adr_i,
                s0_dat_i=>wbs_dat_i,
                s0_dat_o=>wbs_dat_o,
 
                s1_cyc_i=>monitor_dbus.cyc,
                s1_stb_i=>monitor_dbus.stb,
                s1_we_i=>monitor_dbus.we,
                s1_sel_i=>monitor_dbus.sel,
                s1_ack_o=>monitor_dbus.ack,
                s1_adr_i=>monitor_dbus.adr,
                s1_dat_i=>monitor_dbus.wdata,
                s1_dat_o=>monitor_dbus.rdata,
 
                m0_cyc_o=>ram_wb.cyc,
                m0_stb_o=>ram_wb.stb,
                m0_we_o=>ram_wb.we,
                m0_sel_o=>ram_wb.sel,
                m0_ack_i=>ram_wb.ack,
                m0_adr_o=>ram_wb.adr,
                m0_dat_o=>ram_wb.wdata,
                m0_dat_i=>ram_wb.rdata,
 
                m1_cyc_o=>wbm_cyc_o,
                m1_stb_o=>wbm_stb_o,
                m1_we_o=>wbm_we_o,
                m1_sel_o=>wbm_sel_o,
                m1_ack_i=>wbm_ack_i,
                m1_adr_o=>wbm_adr_o,
                m1_dat_o=>wbm_dat_o,
                m1_dat_i=>wbm_dat_i,
 
                m2_cyc_o=>timer_wb.cyc,
                m2_stb_o=>timer_wb.stb,
                m2_we_o=>timer_wb.we,
                m2_sel_o=>timer_wb.sel,
                m2_ack_i=>timer_wb.ack,
                m2_adr_o=>timer_wb.adr,
                m2_dat_o=>timer_wb.wdata,
                m2_dat_i=>timer_wb.rdata,
 
                m3_cyc_o=>coprocessor_wb.cyc,
                m3_stb_o=>coprocessor_wb.stb,
                m3_we_o=>coprocessor_wb.we,
                m3_sel_o=>coprocessor_wb.sel,
                m3_ack_i=>coprocessor_wb.ack,
                m3_adr_o=>coprocessor_wb.adr,
                m3_dat_o=>coprocessor_wb.wdata,
                m3_dat_i=>coprocessor_wb.rdata
        );
 
-- CPU
 
cpu_rst<=cpu_rst_i or rst_i;
 
-- Note: we connect the timer IRQ to 2 CPU channels to test
-- handling of simultaneously arriving interrupt requests.
 
cpu_irq<="00000"&coprocessor_irq&timer_elapsed&timer_elapsed;
 
gen_lxp32u: if not MODEL_LXP32C generate
        lxp32u_top_inst: entity work.lxp32u_top(rtl)
                generic map(
                        DBUS_RMW=>CPU_DBUS_RMW,
                        DIVIDER_EN=>true,
                        MUL_ARCH=>CPU_MUL_ARCH,
                        START_ADDR=>(others=>'0')
                )
                port map(
                        clk_i=>clk_i,
                        rst_i=>cpu_rst,
 
                        lli_re_o=>lli_re,
                        lli_adr_o=>lli_adr,
                        lli_dat_i=>lli_dat,
                        lli_busy_i=>lli_busy,
 
                        dbus_cyc_o=>cpu_dbus.cyc,
                        dbus_stb_o=>cpu_dbus.stb,
                        dbus_we_o=>cpu_dbus.we,
                        dbus_sel_o=>cpu_dbus.sel,
                        dbus_ack_i=>cpu_dbus.ack,
                        dbus_adr_o=>cpu_dbus.adr,
                        dbus_dat_o=>cpu_dbus.wdata,
                        dbus_dat_i=>cpu_dbus.rdata,
 
                        irq_i=>cpu_irq
                );
end generate;
 
gen_lxp32c: if MODEL_LXP32C generate
        lxp32c_top_inst: entity work.lxp32c_top(rtl)
                generic map(
                        DBUS_RMW=>CPU_DBUS_RMW,
                        DIVIDER_EN=>true,
                        IBUS_BURST_SIZE=>16,
                        IBUS_PREFETCH_SIZE=>32,
                        MUL_ARCH=>CPU_MUL_ARCH,
                        START_ADDR=>(others=>'0')
                )
                port map(
                        clk_i=>clk_i,
                        rst_i=>cpu_rst,
 
                        ibus_cyc_o=>cpu_ibus.cyc,
                        ibus_stb_o=>cpu_ibus.stb,
                        ibus_cti_o=>cpu_ibus.cti,
                        ibus_bte_o=>cpu_ibus.bte,
                        ibus_ack_i=>cpu_ibus.ack,
                        ibus_adr_o=>cpu_ibus.adr,
                        ibus_dat_i=>cpu_ibus.dat,
 
                        dbus_cyc_o=>cpu_dbus.cyc,
                        dbus_stb_o=>cpu_dbus.stb,
                        dbus_we_o=>cpu_dbus.we,
                        dbus_sel_o=>cpu_dbus.sel,
                        dbus_ack_i=>cpu_dbus.ack,
                        dbus_adr_o=>cpu_dbus.adr,
                        dbus_dat_o=>cpu_dbus.wdata,
                        dbus_dat_i=>cpu_dbus.rdata,
 
                        irq_i=>cpu_irq
                );
 
        ibus_adapter_inst: entity work.ibus_adapter(rtl)
                port map(
                        clk_i=>clk_i,
                        rst_i=>rst_i,
 
                        ibus_cyc_i=>cpu_ibus.cyc,
                        ibus_stb_i=>cpu_ibus.stb,
                        ibus_cti_i=>cpu_ibus.cti,
                        ibus_bte_i=>cpu_ibus.bte,
                        ibus_ack_o=>cpu_ibus.ack,
                        ibus_adr_i=>cpu_ibus.adr,
                        ibus_dat_o=>cpu_ibus.dat,
 
                        lli_re_o=>lli_re,
                        lli_adr_o=>lli_adr,
                        lli_dat_i=>lli_dat,
                        lli_busy_i=>lli_busy
                );
end generate;
 
-- DBUS monitor
 
dbus_monitor_inst: entity work.dbus_monitor(rtl)
        generic map(
                THROTTLE=>THROTTLE_DBUS
        )
        port map(
                clk_i=>clk_i,
                rst_i=>rst_i,
 
                wbs_cyc_i=>cpu_dbus.cyc,
                wbs_stb_i=>cpu_dbus.stb,
                wbs_we_i=>cpu_dbus.we,
                wbs_sel_i=>cpu_dbus.sel,
                wbs_ack_o=>cpu_dbus.ack,
                wbs_adr_i=>cpu_dbus.adr,
                wbs_dat_i=>cpu_dbus.wdata,
                wbs_dat_o=>cpu_dbus.rdata,
 
                wbm_cyc_o=>monitor_dbus.cyc,
                wbm_stb_o=>monitor_dbus.stb,
                wbm_we_o=>monitor_dbus.we,
                wbm_sel_o=>monitor_dbus.sel,
                wbm_ack_i=>monitor_dbus.ack,
                wbm_adr_o=>monitor_dbus.adr,
                wbm_dat_o=>monitor_dbus.wdata,
                wbm_dat_i=>monitor_dbus.rdata
        );
 
-- Program RAM
 
program_ram_inst: entity work.program_ram(rtl)
        generic map(
                THROTTLE=>THROTTLE_IBUS
        )
        port map(
                clk_i=>clk_i,
                rst_i=>rst_i,
 
                wbs_cyc_i=>ram_wb.cyc,
                wbs_stb_i=>ram_wb.stb,
                wbs_we_i=>ram_wb.we,
                wbs_sel_i=>ram_wb.sel,
                wbs_ack_o=>ram_wb.ack,
                wbs_adr_i=>ram_wb.adr,
                wbs_dat_i=>ram_wb.wdata,
                wbs_dat_o=>ram_wb.rdata,
 
                lli_re_i=>lli_re,
                lli_adr_i=>lli_adr,
                lli_dat_o=>lli_dat,
                lli_busy_o=>lli_busy
        );
 
-- Timer
 
timer_inst: entity work.timer(rtl)
        port map(
                clk_i=>clk_i,
                rst_i=>rst_i,
 
                wbs_cyc_i=>timer_wb.cyc,
                wbs_stb_i=>timer_wb.stb,
                wbs_we_i=>timer_wb.we,
                wbs_sel_i=>timer_wb.sel,
                wbs_ack_o=>timer_wb.ack,
                wbs_adr_i=>timer_wb.adr,
                wbs_dat_i=>timer_wb.wdata,
                wbs_dat_o=>timer_wb.rdata,
 
                elapsed_o=>timer_elapsed
        );
 
-- Coprocessor
 
coprocessor_inst: entity work.coprocessor(rtl)
        port map(
                clk_i=>clk_i,
                rst_i=>rst_i,
 
                wbs_cyc_i=>coprocessor_wb.cyc,
                wbs_stb_i=>coprocessor_wb.stb,
                wbs_we_i=>coprocessor_wb.we,
                wbs_sel_i=>coprocessor_wb.sel,
                wbs_ack_o=>coprocessor_wb.ack,
                wbs_adr_i=>coprocessor_wb.adr,
                wbs_dat_i=>coprocessor_wb.wdata,
                wbs_dat_o=>coprocessor_wb.rdata,
 
                irq_o=>coprocessor_irq
        );
 
end architecture;

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Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [platform/] [platform.vhd] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	ring0_mipt	`---------------------------------------------------------------------`
2			`-- LXP32 platform top-level design unit`
3			`--`
4			`-- Part of the LXP32 test platform`
5			`--`
6			`-- Copyright (c) 2016 by Alex I. Kuznetsov`
7			`--`
8			`-- A SoC-like simulation platform for the LXP32 CPU, containing`
9			`-- a few peripherals such as program RAM, timer and coprocessor.`
10			`--`
11			`-- Note: regardless of whether this description is synthesizable,`
12			`-- it was designed exclusively for simulation purposes.`
13			`---------------------------------------------------------------------`
14
15			`library ieee;`
16			`use ieee.std_logic_1164.all;`
17
18			`entity platform is`
19			`generic(`
20			`CPU_DBUS_RMW: boolean;`
21			`CPU_MUL_ARCH: string;`
22			`MODEL_LXP32C: boolean;`
23			`THROTTLE_DBUS: boolean;`
24			`THROTTLE_IBUS: boolean`
25			`);`
26			`port(`
27			`clk_i: in std_logic;`
28			`rst_i: in std_logic;`
29			`cpu_rst_i: in std_logic;`
30
31			`wbm_cyc_o: out std_logic;`
32			`wbm_stb_o: out std_logic;`
33			`wbm_we_o: out std_logic;`
34			`wbm_sel_o: out std_logic_vector(3 downto 0);`
35			`wbm_ack_i: in std_logic;`
36			`wbm_adr_o: out std_logic_vector(27 downto 2);`
37			`wbm_dat_o: out std_logic_vector(31 downto 0);`
38			`wbm_dat_i: in std_logic_vector(31 downto 0);`
39
40			`wbs_cyc_i: in std_logic;`
41			`wbs_stb_i: in std_logic;`
42			`wbs_we_i: in std_logic;`
43			`wbs_sel_i: in std_logic_vector(3 downto 0);`
44			`wbs_ack_o: out std_logic;`
45			`wbs_adr_i: in std_logic_vector(31 downto 2);`
46			`wbs_dat_i: in std_logic_vector(31 downto 0);`
47			`wbs_dat_o: out std_logic_vector(31 downto 0);`
48
49			`gp_io: inout std_logic_vector(31 downto 0)`
50			`);`
51			`end entity;`
52
53			`architecture rtl of platform is`
54
55			`type wbm_type is record`
56			`cyc: std_logic;`
57			`stb: std_logic;`
58			`we: std_logic;`
59			`sel: std_logic_vector(3 downto 0);`
60			`ack: std_logic;`
61			`adr: std_logic_vector(31 downto 2);`
62			`wdata: std_logic_vector(31 downto 0);`
63			`rdata: std_logic_vector(31 downto 0);`
64			`end record;`
65
66			`type wbs_type is record`
67			`cyc: std_logic;`
68			`stb: std_logic;`
69			`we: std_logic;`
70			`sel: std_logic_vector(3 downto 0);`
71			`ack: std_logic;`
72			`adr: std_logic_vector(27 downto 2);`
73			`wdata: std_logic_vector(31 downto 0);`
74			`rdata: std_logic_vector(31 downto 0);`
75			`end record;`
76
77			`type ibus_type is record`
78			`cyc: std_logic;`
79			`stb: std_logic;`
80			`cti: std_logic_vector(2 downto 0);`
81			`bte: std_logic_vector(1 downto 0);`
82			`ack: std_logic;`
83			`adr: std_logic_vector(29 downto 0);`
84			`dat: std_logic_vector(31 downto 0);`
85			`end record;`
86
87			`signal cpu_rst: std_logic;`
88			`signal cpu_irq: std_logic_vector(7 downto 0);`
89			`signal cpu_dbus: wbm_type;`
90			`signal cpu_ibus: ibus_type;`
91
92			`signal lli_re: std_logic;`
93			`signal lli_adr: std_logic_vector(29 downto 0);`
94			`signal lli_dat: std_logic_vector(31 downto 0);`
95			`signal lli_busy: std_logic;`
96
97			`signal monitor_dbus: wbm_type;`
98
99			`signal ram_wb: wbs_type;`
100
101			`signal timer_wb: wbs_type;`
102			`signal timer_elapsed: std_logic;`
103
104			`signal coprocessor_wb: wbs_type;`
105			`signal coprocessor_irq: std_logic;`
106
107			`begin`
108
109			`-- Interconnect`
110
111			`intercon_inst: entity work.intercon(rtl)`
112			`port map(`
113			`clk_i=>clk_i,`
114			`rst_i=>rst_i,`
115
116			`s0_cyc_i=>wbs_cyc_i,`
117			`s0_stb_i=>wbs_stb_i,`
118			`s0_we_i=>wbs_we_i,`
119			`s0_sel_i=>wbs_sel_i,`
120			`s0_ack_o=>wbs_ack_o,`
121			`s0_adr_i=>wbs_adr_i,`
122			`s0_dat_i=>wbs_dat_i,`
123			`s0_dat_o=>wbs_dat_o,`
124
125			`s1_cyc_i=>monitor_dbus.cyc,`
126			`s1_stb_i=>monitor_dbus.stb,`
127			`s1_we_i=>monitor_dbus.we,`
128			`s1_sel_i=>monitor_dbus.sel,`
129			`s1_ack_o=>monitor_dbus.ack,`
130			`s1_adr_i=>monitor_dbus.adr,`
131			`s1_dat_i=>monitor_dbus.wdata,`
132			`s1_dat_o=>monitor_dbus.rdata,`
133
134			`m0_cyc_o=>ram_wb.cyc,`
135			`m0_stb_o=>ram_wb.stb,`
136			`m0_we_o=>ram_wb.we,`
137			`m0_sel_o=>ram_wb.sel,`
138			`m0_ack_i=>ram_wb.ack,`
139			`m0_adr_o=>ram_wb.adr,`
140			`m0_dat_o=>ram_wb.wdata,`
141			`m0_dat_i=>ram_wb.rdata,`
142
143			`m1_cyc_o=>wbm_cyc_o,`
144			`m1_stb_o=>wbm_stb_o,`
145			`m1_we_o=>wbm_we_o,`
146			`m1_sel_o=>wbm_sel_o,`
147			`m1_ack_i=>wbm_ack_i,`
148			`m1_adr_o=>wbm_adr_o,`
149			`m1_dat_o=>wbm_dat_o,`
150			`m1_dat_i=>wbm_dat_i,`
151
152			`m2_cyc_o=>timer_wb.cyc,`
153			`m2_stb_o=>timer_wb.stb,`
154			`m2_we_o=>timer_wb.we,`
155			`m2_sel_o=>timer_wb.sel,`
156			`m2_ack_i=>timer_wb.ack,`
157			`m2_adr_o=>timer_wb.adr,`
158			`m2_dat_o=>timer_wb.wdata,`
159			`m2_dat_i=>timer_wb.rdata,`
160
161			`m3_cyc_o=>coprocessor_wb.cyc,`
162			`m3_stb_o=>coprocessor_wb.stb,`
163			`m3_we_o=>coprocessor_wb.we,`
164			`m3_sel_o=>coprocessor_wb.sel,`
165			`m3_ack_i=>coprocessor_wb.ack,`
166			`m3_adr_o=>coprocessor_wb.adr,`
167			`m3_dat_o=>coprocessor_wb.wdata,`
168			`m3_dat_i=>coprocessor_wb.rdata`
169			`);`
170
171			`-- CPU`
172
173			`cpu_rst<=cpu_rst_i or rst_i;`
174
175			`-- Note: we connect the timer IRQ to 2 CPU channels to test`
176			`-- handling of simultaneously arriving interrupt requests.`
177
178			`cpu_irq<="00000"&coprocessor_irq&timer_elapsed&timer_elapsed;`
179
180			`gen_lxp32u: if not MODEL_LXP32C generate`
181			`lxp32u_top_inst: entity work.lxp32u_top(rtl)`
182			`generic map(`
183			`DBUS_RMW=>CPU_DBUS_RMW,`
184			`DIVIDER_EN=>true,`
185			`MUL_ARCH=>CPU_MUL_ARCH,`
186			`START_ADDR=>(others=>'0')`
187			`)`
188			`port map(`
189			`clk_i=>clk_i,`
190			`rst_i=>cpu_rst,`
191
192			`lli_re_o=>lli_re,`
193			`lli_adr_o=>lli_adr,`
194			`lli_dat_i=>lli_dat,`
195			`lli_busy_i=>lli_busy,`
196
197			`dbus_cyc_o=>cpu_dbus.cyc,`
198			`dbus_stb_o=>cpu_dbus.stb,`
199			`dbus_we_o=>cpu_dbus.we,`
200			`dbus_sel_o=>cpu_dbus.sel,`
201			`dbus_ack_i=>cpu_dbus.ack,`
202			`dbus_adr_o=>cpu_dbus.adr,`
203			`dbus_dat_o=>cpu_dbus.wdata,`
204			`dbus_dat_i=>cpu_dbus.rdata,`
205
206			`irq_i=>cpu_irq`
207			`);`
208			`end generate;`
209
210			`gen_lxp32c: if MODEL_LXP32C generate`
211			`lxp32c_top_inst: entity work.lxp32c_top(rtl)`
212			`generic map(`
213			`DBUS_RMW=>CPU_DBUS_RMW,`
214			`DIVIDER_EN=>true,`
215			`IBUS_BURST_SIZE=>16,`
216			`IBUS_PREFETCH_SIZE=>32,`
217			`MUL_ARCH=>CPU_MUL_ARCH,`
218			`START_ADDR=>(others=>'0')`
219			`)`
220			`port map(`
221			`clk_i=>clk_i,`
222			`rst_i=>cpu_rst,`
223
224			`ibus_cyc_o=>cpu_ibus.cyc,`
225			`ibus_stb_o=>cpu_ibus.stb,`
226			`ibus_cti_o=>cpu_ibus.cti,`
227			`ibus_bte_o=>cpu_ibus.bte,`
228			`ibus_ack_i=>cpu_ibus.ack,`
229			`ibus_adr_o=>cpu_ibus.adr,`
230			`ibus_dat_i=>cpu_ibus.dat,`
231
232			`dbus_cyc_o=>cpu_dbus.cyc,`
233			`dbus_stb_o=>cpu_dbus.stb,`
234			`dbus_we_o=>cpu_dbus.we,`
235			`dbus_sel_o=>cpu_dbus.sel,`
236			`dbus_ack_i=>cpu_dbus.ack,`
237			`dbus_adr_o=>cpu_dbus.adr,`
238			`dbus_dat_o=>cpu_dbus.wdata,`
239			`dbus_dat_i=>cpu_dbus.rdata,`
240
241			`irq_i=>cpu_irq`
242			`);`
243
244			`ibus_adapter_inst: entity work.ibus_adapter(rtl)`
245			`port map(`
246			`clk_i=>clk_i,`
247			`rst_i=>rst_i,`
248
249			`ibus_cyc_i=>cpu_ibus.cyc,`
250			`ibus_stb_i=>cpu_ibus.stb,`
251			`ibus_cti_i=>cpu_ibus.cti,`
252			`ibus_bte_i=>cpu_ibus.bte,`
253			`ibus_ack_o=>cpu_ibus.ack,`
254			`ibus_adr_i=>cpu_ibus.adr,`
255			`ibus_dat_o=>cpu_ibus.dat,`
256
257			`lli_re_o=>lli_re,`
258			`lli_adr_o=>lli_adr,`
259			`lli_dat_i=>lli_dat,`
260			`lli_busy_i=>lli_busy`
261			`);`
262			`end generate;`
263
264			`-- DBUS monitor`
265
266			`dbus_monitor_inst: entity work.dbus_monitor(rtl)`
267			`generic map(`
268			`THROTTLE=>THROTTLE_DBUS`
269			`)`
270			`port map(`
271			`clk_i=>clk_i,`
272			`rst_i=>rst_i,`
273
274			`wbs_cyc_i=>cpu_dbus.cyc,`
275			`wbs_stb_i=>cpu_dbus.stb,`
276			`wbs_we_i=>cpu_dbus.we,`
277			`wbs_sel_i=>cpu_dbus.sel,`
278			`wbs_ack_o=>cpu_dbus.ack,`
279			`wbs_adr_i=>cpu_dbus.adr,`
280			`wbs_dat_i=>cpu_dbus.wdata,`
281			`wbs_dat_o=>cpu_dbus.rdata,`
282
283			`wbm_cyc_o=>monitor_dbus.cyc,`
284			`wbm_stb_o=>monitor_dbus.stb,`
285			`wbm_we_o=>monitor_dbus.we,`
286			`wbm_sel_o=>monitor_dbus.sel,`
287			`wbm_ack_i=>monitor_dbus.ack,`
288			`wbm_adr_o=>monitor_dbus.adr,`
289			`wbm_dat_o=>monitor_dbus.wdata,`
290			`wbm_dat_i=>monitor_dbus.rdata`
291			`);`
292
293			`-- Program RAM`
294
295			`program_ram_inst: entity work.program_ram(rtl)`
296			`generic map(`
297			`THROTTLE=>THROTTLE_IBUS`
298			`)`
299			`port map(`
300			`clk_i=>clk_i,`
301			`rst_i=>rst_i,`
302
303			`wbs_cyc_i=>ram_wb.cyc,`
304			`wbs_stb_i=>ram_wb.stb,`
305			`wbs_we_i=>ram_wb.we,`
306			`wbs_sel_i=>ram_wb.sel,`
307			`wbs_ack_o=>ram_wb.ack,`
308			`wbs_adr_i=>ram_wb.adr,`
309			`wbs_dat_i=>ram_wb.wdata,`
310			`wbs_dat_o=>ram_wb.rdata,`
311
312			`lli_re_i=>lli_re,`
313			`lli_adr_i=>lli_adr,`
314			`lli_dat_o=>lli_dat,`
315			`lli_busy_o=>lli_busy`
316			`);`
317
318			`-- Timer`
319
320			`timer_inst: entity work.timer(rtl)`
321			`port map(`
322			`clk_i=>clk_i,`
323			`rst_i=>rst_i,`
324
325			`wbs_cyc_i=>timer_wb.cyc,`
326			`wbs_stb_i=>timer_wb.stb,`
327			`wbs_we_i=>timer_wb.we,`
328			`wbs_sel_i=>timer_wb.sel,`
329			`wbs_ack_o=>timer_wb.ack,`
330			`wbs_adr_i=>timer_wb.adr,`
331			`wbs_dat_i=>timer_wb.wdata,`
332			`wbs_dat_o=>timer_wb.rdata,`
333
334			`elapsed_o=>timer_elapsed`
335			`);`
336
337			`-- Coprocessor`
338
339			`coprocessor_inst: entity work.coprocessor(rtl)`
340			`port map(`
341			`clk_i=>clk_i,`
342			`rst_i=>rst_i,`
343
344			`wbs_cyc_i=>coprocessor_wb.cyc,`
345			`wbs_stb_i=>coprocessor_wb.stb,`
346			`wbs_we_i=>coprocessor_wb.we,`
347			`wbs_sel_i=>coprocessor_wb.sel,`
348			`wbs_ack_o=>coprocessor_wb.ack,`
349			`wbs_adr_i=>coprocessor_wb.adr,`
350			`wbs_dat_i=>coprocessor_wb.wdata,`
351			`wbs_dat_o=>coprocessor_wb.rdata,`
352
353			`irq_o=>coprocessor_irq`
354			`);`
355
356			`end architecture;`