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[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [tb/] [tb_pkg_body.vhd] - Blame information for rev 9

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1 9 ring0_mipt
---------------------------------------------------------------------
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-- LXP32 testbench package body
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--
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-- Part of the LXP32 testbench
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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-- Auxiliary package body for the LXP32 testbench
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---------------------------------------------------------------------
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use std.textio.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.common_pkg.all;
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package body tb_pkg is
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        procedure load_ram(
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                filename: string;
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                signal clk: in std_logic;
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                signal soc_in: out soc_wbs_in_type;
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                signal soc_out: in soc_wbs_out_type
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        ) is
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                file f: text open read_mode is filename;
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                variable i: integer:=0;
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                variable l: line;
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                variable v: bit_vector(31 downto 0);
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        begin
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                wait until rising_edge(clk);
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                report "Loading program RAM from """&filename&"""";
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                while not endfile(f) loop
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                        readline(f,l);
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                        read(l,v);
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                        assert i<c_max_program_size report "Error: program size is too large" severity failure;
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                        soc_in.cyc<='1';
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                        soc_in.stb<='1';
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                        soc_in.we<='1';
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                        soc_in.sel<=(others=>'1');
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                        soc_in.adr<=std_logic_vector(to_unsigned(i,30));
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                        soc_in.dat<=to_stdlogicvector(v);
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                        wait until rising_edge(clk) and soc_out.ack='1';
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                        i:=i+1;
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                end loop;
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                report integer'image(i)&" words loaded from """&filename&"""";
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                soc_in.cyc<='0';
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                soc_in.stb<='0';
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                wait until rising_edge(clk);
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        end procedure;
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        procedure run_test(
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                filename: string;
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                signal clk: in std_logic;
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                signal globals: out soc_globals_type;
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                signal soc_in: out soc_wbs_in_type;
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                signal soc_out: in soc_wbs_out_type;
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                signal result: in monitor_out_type
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        ) is
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        begin
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                -- Assert SoC and CPU resets
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                wait until rising_edge(clk);
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                globals.rst_i<='1';
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                globals.cpu_rst_i<='1';
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                wait until rising_edge(clk);
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                -- Deassert SoC reset, leave CPU in reset state for now
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                globals.rst_i<='0';
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                wait until rising_edge(clk);
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                -- Load RAM
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                load_ram(filename,clk,soc_in,soc_out);
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                -- Deassert CPU reset
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                globals.cpu_rst_i<='0';
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                while result.valid/='1' loop
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                        wait until rising_edge(clk);
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                end loop;
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                -- Analyze result
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                if result.data=X"00000001" then
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                        report "TEST """&filename&""" RESULT: SUCCESS (return code 0x"&
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                                hex_string(result.data)&")";
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                else
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                        report "TEST """&filename&""" RESULT: FAILURE (return code 0x"&
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                                hex_string(result.data)&")" severity failure;
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                end if;
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        end procedure;
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end package body;

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