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[/] [mblite/] [trunk/] [designs/] [core_syn/] [README] - Blame information for rev 2

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1 2 takar
Design: core
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Description: The memory organization is as follows
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core
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|
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`- imem
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|
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`- dmem
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The dmem output is tied to the testbench for debugging
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purposes.
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The memory is preloaded with the hello world program
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- MAKE SURE THE SIMULATOR IS SET TO TIME RESOLUTION OF 1 PS
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- REPLACE mblite_soc_*.vhd WITH THE GENERATED VHDL NETLIST
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- OPTIONALLY LOAD THE STANDARD DELAY FORMAT FILE IN MODELSIM
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- THE TOOL mblite/sw/util/bin2rom CAN BE USED TO GENERATE
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  THE INTIALIZATION ASSIGNMENT FROM A BINARY FORMAT

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