OpenCores
URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [designs/] [core_wb/] [testbench.vhd] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 takar
----------------------------------------------------------------------------------------------
2
--
3
--      Input file         : config_Pkg.vhd
4
--      Design name        : config_Pkg
5
--      Author             : Tamar Kranenburg
6
--      Company            : Delft University of Technology
7
--                         : Faculty EEMCS, Department ME&CE
8
--                         : Systems and Circuits group
9
--
10
--      Description        : Testbench instantiates core, data memory, instruction memory
11
--                           and a character device.
12
--
13
----------------------------------------------------------------------------------------------
14
 
15
LIBRARY ieee;
16
USE ieee.std_logic_1164.ALL;
17
USE ieee.std_logic_unsigned.ALL;
18
 
19
LIBRARY mblite;
20
USE mblite.config_Pkg.ALL;
21
USE mblite.core_Pkg.ALL;
22
USE mblite.std_Pkg.ALL;
23
 
24
use std.textio.all;
25
 
26
ENTITY testbench IS
27
END testbench;
28
 
29
ARCHITECTURE arch OF testbench IS
30
 
31
    SIGNAL imem_o : imem_out_type;
32
    SIGNAL imem_i : imem_in_type;
33
 
34
    SIGNAL wb_o : wb_mst_out_type;
35
    SIGNAL wb_i : wb_mst_in_type;
36
 
37 6 takar
    SIGNAL sys_clk_i : std_logic := '0';
38
    SIGNAL sys_int_i : std_logic;
39
    SIGNAL sys_rst_i : std_logic;
40 2 takar
 
41 6 takar
    CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
42
    SIGNAL std_out_ack : std_logic;
43 2 takar
 
44 6 takar
    SIGNAL stdo_ena : std_logic;
45 2 takar
 
46 6 takar
    SIGNAL dmem_ena : std_logic;
47
    SIGNAL dmem_dat : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
48
    SIGNAL dmem_sel : std_logic_vector(3 DOWNTO 0);
49 2 takar
 
50
    CONSTANT rom_size : integer := 16;
51
    CONSTANT ram_size : integer := 16;
52
 
53
BEGIN
54
 
55
    sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
56
    sys_rst_i <= '1' AFTER 0 ps, '0' AFTER  150000 ps;
57
    sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
58
 
59
    timeout: PROCESS(sys_clk_i)
60
    BEGIN
61
        IF NOW = 10 ms THEN
62
            report "TIMEOUT" SEVERITY FAILURE;
63
        END IF;
64
 
65
        -- BREAK ON EXIT (0xB8000000)
66
        IF compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' THEN
67
            -- Make sure the simulator finishes when an error is encountered.
68
            -- For modelsim: see menu Simulate -> Runtime options -> Assertions
69
            REPORT "FINISHED" SEVERITY FAILURE;
70
        END IF;
71
    END PROCESS;
72
 
73
    -- Character device
74
    wb_stdio_slave: PROCESS(sys_clk_i)
75
        VARIABLE s    : line;
76 6 takar
        VARIABLE byte : std_logic_vector(7 DOWNTO 0);
77 2 takar
        VARIABLE char : character;
78
    BEGIN
79
        IF rising_edge(sys_clk_i) THEN
80
            IF (wb_o.stb_o AND wb_o.cyc_o AND compare(wb_o.adr_o, std_out_adr)) = '1' THEN
81
                IF wb_o.we_o = '1' AND std_out_ack = '0' THEN
82
                -- WRITE STDOUT
83
                    std_out_ack <= '1';
84
                    CASE wb_o.sel_o IS
85
                        WHEN "0001" => byte := wb_o.dat_o( 7 DOWNTO  0);
86
                        WHEN "0010" => byte := wb_o.dat_o(15 DOWNTO  8);
87
                        WHEN "0100" => byte := wb_o.dat_o(23 DOWNTO 16);
88
                        WHEN "1000" => byte := wb_o.dat_o(31 DOWNTO 24);
89
                        WHEN OTHERS => NULL;
90
                    END CASE;
91
                    char := character'val(my_conv_integer(byte));
92
                    IF byte = X"0D" THEN
93
                        -- Ignore character 13
94
                    ELSIF byte = X"0A" THEN
95
                        -- Writeline on character 10 (newline)
96
                        writeline(output, s);
97
                    ELSE
98
                        -- Write to buffer
99
                        write(s, char);
100
                    END IF;
101
                ELSIF std_out_ack = '0' THEN
102
                    std_out_ack <= '1';
103
                END IF;
104
            ELSE
105
                std_out_ack <= '0';
106
            END IF;
107
        END IF;
108
 
109
    END PROCESS;
110
 
111
    wb_i.clk_i <= sys_clk_i;
112
    wb_i.rst_i <= sys_rst_i;
113
    wb_i.int_i <= sys_int_i;
114
 
115
    dmem_ena <= wb_o.stb_o AND wb_o.cyc_o AND NOT compare(wb_o.adr_o, std_out_adr);
116
 
117
    PROCESS(wb_o.stb_o, wb_o.cyc_o, std_out_ack, wb_o.adr_o)
118
    BEGIN
119
        IF NOT compare(wb_o.adr_o, std_out_adr) = '1' THEN
120
            wb_i.ack_i <= wb_o.stb_o AND wb_o.cyc_o AFTER 2 ns;
121
        ELSE
122
            wb_i.ack_i <= std_out_ack AFTER 22 ns;
123
        END IF;
124
    END PROCESS;
125
 
126
    imem : sram GENERIC MAP
127
    (
128
        WIDTH => CFG_IMEM_WIDTH,
129
        SIZE => rom_size - 2
130
    )
131
    PORT MAP
132
    (
133
        dat_o => imem_i.dat_i,
134
        dat_i => "00000000000000000000000000000000",
135
        adr_i => imem_o.adr_o(rom_size - 1 DOWNTO 2),
136
        wre_i => '0',
137
        ena_i => imem_o.ena_o,
138
        clk_i => sys_clk_i
139
    );
140
 
141
    dmem_sel <= wb_o.sel_o WHEN wb_o.we_o = '1' ELSE (OTHERS => '0');
142
    wb_i.dat_i <= X"61616161" WHEN std_out_ack = '1' ELSE dmem_dat;
143
 
144
    dmem : sram_4en GENERIC MAP
145
    (
146
        WIDTH => CFG_DMEM_WIDTH,
147
        SIZE => ram_size - 2
148
    )
149
    PORT MAP
150
    (
151
        dat_o => dmem_dat,
152
        dat_i => wb_o.dat_o,
153
        adr_i => wb_o.adr_o(ram_size - 1 DOWNTO 2),
154
        wre_i => dmem_sel,
155
        ena_i => dmem_ena,
156
        clk_i => sys_clk_i
157
    );
158
 
159
    core_wb0 : core_wb PORT MAP
160
    (
161
        imem_o => imem_o,
162
        wb_o   => wb_o,
163
        imem_i => imem_i,
164
        wb_i   => wb_i
165
    );
166
 
167
END arch;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.