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[/] [mblite/] [trunk/] [hw/] [core/] [core_address_decoder.vhd] - Blame information for rev 6

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Line No. Rev Author Line
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----------------------------------------------------------------------------------------------
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--
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--      Input file         : core_address_decoder.vhd
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--      Design name        : core_address_decoder
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description        : Wishbone adapter for the MB-Lite microprocessor
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--
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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LIBRARY mblite;
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USE mblite.config_Pkg.ALL;
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USE mblite.core_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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ENTITY core_address_decoder IS GENERIC
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(
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    G_NUM_SLAVES : positive := CFG_NUM_SLAVES;
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    G_MEMORY_MAP : memory_map_type := CFG_MEMORY_MAP
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);
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PORT
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(
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    m_dmem_i : OUT dmem_in_type;
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    s_dmem_o : OUT dmem_out_array_type(G_NUM_SLAVES - 1 DOWNTO 0);
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    m_dmem_o : IN dmem_out_type;
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    s_dmem_i : IN dmem_in_array_type(G_NUM_SLAVES - 1 DOWNTO 0);
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    clk_i : std_logic
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);
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END core_address_decoder;
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ARCHITECTURE arch OF core_address_decoder IS
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    -- Decodes the address based on the memory map. Returns "1" if 0 or 1 slave is attached.
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    FUNCTION decode(adr : std_logic_vector) RETURN std_logic_vector IS
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        VARIABLE result : std_logic_vector(G_NUM_SLAVES - 1 DOWNTO 0);
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    BEGIN
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        result := (OTHERS => '1');
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        IF G_NUM_SLAVES > 1 AND notx(adr) THEN
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            FOR i IN G_NUM_SLAVES - 1 DOWNTO 0 LOOP
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                IF (adr >= G_MEMORY_MAP(i) AND adr < G_MEMORY_MAP(i+1)) THEN
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                    result(i) := '1';
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                ELSE
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                    result(i) := '0';
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                END IF;
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            END LOOP;
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        END IF;
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        RETURN result;
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    END FUNCTION;
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    FUNCTION demux(dmem_i : dmem_in_array_type; ce, r_ce : std_logic_vector) RETURN dmem_in_type IS
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        VARIABLE dmem : dmem_in_type;
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    BEGIN
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        dmem := dmem_i(0);
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        IF notx(ce) THEN
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            FOR i IN G_NUM_SLAVES - 1 DOWNTO 0 LOOP
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                IF ce(i) = '1' THEN
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                    dmem.ena_i := dmem_i(i).ena_i;
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                END IF;
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                IF r_ce(i) = '1' THEN
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                    dmem.dat_i := dmem_i(i).dat_i;
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                END IF;
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            END LOOP;
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        END IF;
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        RETURN dmem;
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    END FUNCTION;
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    SIGNAL r_ce, ce : std_logic_vector(G_NUM_SLAVES - 1 DOWNTO 0) := (OTHERS => '1');
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BEGIN
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    ce <= decode(m_dmem_o.adr_o);
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    m_dmem_i <= demux(s_dmem_i, ce, r_ce);
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    CON: FOR i IN G_NUM_SLAVES-1 DOWNTO 0 GENERATE
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    BEGIN
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        s_dmem_o(i).dat_o <= m_dmem_o.dat_o;
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        s_dmem_o(i).adr_o <= m_dmem_o.adr_o;
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        s_dmem_o(i).sel_o <= m_dmem_o.sel_o;
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        s_dmem_o(i).we_o  <= m_dmem_o.we_o AND ce(i);
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        s_dmem_o(i).ena_o <= m_dmem_o.ena_o AND ce(i);
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    END GENERATE;
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    PROCESS(clk_i)
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    BEGIN
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        IF rising_edge(clk_i) THEN
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            r_ce <= ce;
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        END IF;
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    END PROCESS;
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END arch;

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