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[/] [mblite/] [trunk/] [hw/] [core/] [core_address_decoder.vhd] - Blame information for rev 8

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----------------------------------------------------------------------------------------------
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--
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--      Input file         : core_address_decoder.vhd
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--      Design name        : core_address_decoder
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description        : Wishbone adapter for the MB-Lite microprocessor
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--
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----------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mblite;
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use mblite.config_Pkg.all;
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use mblite.core_Pkg.all;
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use mblite.std_Pkg.all;
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entity core_address_decoder is generic
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(
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    G_NUM_SLAVES : positive := CFG_NUM_SLAVES;
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    G_MEMORY_MAP : memory_map_type := CFG_MEMORY_MAP
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);
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port
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(
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    m_dmem_i : out dmem_in_type;
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    s_dmem_o : out dmem_out_array_type(G_NUM_SLAVES - 1 downto 0);
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    m_dmem_o : in dmem_out_type;
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    s_dmem_i : in dmem_in_array_type(G_NUM_SLAVES - 1 downto 0);
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    clk_i : std_logic
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);
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end core_address_decoder;
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architecture arch of core_address_decoder is
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    -- Decodes the address based on the memory map. Returns "1" if 0 or 1 slave is attached.
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    function decode(adr : std_logic_vector) return std_logic_vector is
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        variable result : std_logic_vector(G_NUM_SLAVES - 1 downto 0);
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    begin
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        if G_NUM_SLAVES > 1 and notx(adr) then
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            for i in G_NUM_SLAVES - 1 downto 0 loop
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                if (adr >= G_MEMORY_MAP(i) and adr < G_MEMORY_MAP(i+1)) then
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                    result(i) := '1';
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                else
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                    result(i) := '0';
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                end if;
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            end loop;
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        else
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            result := (others => '1');
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        end if;
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        return result;
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    end function;
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    function demux(dmem_i : dmem_in_array_type; ce, r_ce : std_logic_vector) return dmem_in_type is
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        variable dmem : dmem_in_type;
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    begin
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        dmem := dmem_i(0);
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        if notx(ce) then
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            for i in G_NUM_SLAVES - 1 downto 0 loop
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                if ce(i) = '1' then
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                    dmem.ena_i := dmem_i(i).ena_i;
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                end if;
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                if r_ce(i) = '1' then
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                    dmem.dat_i := dmem_i(i).dat_i;
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                end if;
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            end loop;
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        end if;
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        return dmem;
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    end function;
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    signal r_ce, ce : std_logic_vector(G_NUM_SLAVES - 1 downto 0) := (others => '1');
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begin
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    ce <= decode(m_dmem_o.adr_o);
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    m_dmem_i <= demux(s_dmem_i, ce, r_ce);
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    CON: for i in G_NUM_SLAVES-1 downto 0 generate
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    begin
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        s_dmem_o(i).dat_o <= m_dmem_o.dat_o;
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        s_dmem_o(i).adr_o <= m_dmem_o.adr_o;
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        s_dmem_o(i).sel_o <= m_dmem_o.sel_o;
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        s_dmem_o(i).we_o  <= m_dmem_o.we_o and ce(i);
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        s_dmem_o(i).ena_o <= m_dmem_o.ena_o and ce(i);
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    end generate;
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    process(clk_i)
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    begin
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        if rising_edge(clk_i) then
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            r_ce <= ce;
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        end if;
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    end process;
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end arch;

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