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[/] [mblite/] [trunk/] [hw/] [core/] [core_wb.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 takar
----------------------------------------------------------------------------------------------
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--
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--      Input file         : core_wb.vhd
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--      Design name        : core_wb
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description        : Top level module of the MB-Lite microprocessor with connected
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--                           wishbone data bus
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--
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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LIBRARY mblite;
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USE mblite.config_Pkg.ALL;
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USE mblite.core_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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ENTITY core_wb IS GENERIC
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(
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    G_INTERRUPT  : boolean := CFG_INTERRUPT;
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    G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
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    G_USE_BARREL : boolean := CFG_USE_BARREL;
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    G_DEBUG      : boolean := CFG_DEBUG
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);
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PORT
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(
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    imem_o : OUT imem_out_type;
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    wb_o   : OUT wb_mst_out_type;
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    imem_i : IN imem_in_type;
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    wb_i   : IN wb_mst_in_type
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);
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END core_wb;
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ARCHITECTURE arch OF core_wb IS
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    SIGNAL dmem_i : dmem_in_type;
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    SIGNAL dmem_o : dmem_out_type;
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BEGIN
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    wb_adapter0 : core_wb_adapter PORT MAP
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    (
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        dmem_i => dmem_i,
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        wb_o   => wb_o,
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        dmem_o => dmem_o,
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        wb_i   => wb_i
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    );
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    core0 : core GENERIC MAP
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    (
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        G_INTERRUPT  => G_INTERRUPT,
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        G_USE_HW_MUL => G_USE_HW_MUL,
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        G_USE_BARREL => G_USE_BARREL,
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        G_DEBUG      => G_DEBUG
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    )
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    PORT MAP
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    (
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        imem_o => imem_o,
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        dmem_o => dmem_o,
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        imem_i => imem_i,
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        dmem_i => dmem_i,
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        int_i  => wb_i.int_i,
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        rst_i  => wb_i.rst_i,
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        clk_i  => wb_i.clk_i
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    );
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END arch;

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