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[/] [mblite/] [trunk/] [hw/] [std/] [sram.vhd] - Blame information for rev 8

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----------------------------------------------------------------------------------------------
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--
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--      Input file         : sram.vhd
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--      Design name        : sram
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description        : Single Port Synchronous Random Access Memory
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--
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----------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mblite;
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use mblite.std_Pkg.all;
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entity sram is generic
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(
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    WIDTH : positive := 32;
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    SIZE  : positive := 16
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);
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port
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(
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    dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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    dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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    adr_i : in std_logic_vector(SIZE - 1 downto 0);
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    wre_i : in std_logic;
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    ena_i : in std_logic;
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    clk_i : in std_logic
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);
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end sram;
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architecture arch of sram is
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    type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
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    signal ram :  ram_type;
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begin
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    process(clk_i)
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    begin
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        if rising_edge(clk_i) then
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            if ena_i = '1' then
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                if wre_i = '1' then
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                   ram(my_conv_integer(adr_i)) <= dat_i;
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                end if;
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                dat_o <= ram(my_conv_integer(adr_i));
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            end if;
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        end if;
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    end process;
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end arch;

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