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[/] [mesi_isc/] [trunk/] [sim/] [iverilog.log] - Blame information for rev 3

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1 3 yaira
Using language generation: IEEE1364-2005,no-specify,xtypes,icarus-misc
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PARSING INPUT
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LOCATING TOP-LEVEL MODULES
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   mesi_isc_tb
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ELABORATING DESIGN
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RUNNING FUNCTORS
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 ... 1 iterations deleted 372 dangling signals and 0 events.
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 ... 2 iterations deleted 372 dangling signals and 69 events.
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CALCULATING ISLANDS
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CODE GENERATION
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 ... invoking target_design
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STATISTICS
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lex_string: add_count=683 hit_count=3356
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Icarus Verilog version 0.9.3  (v0_9_3)
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Copyright 1998-2010 Stephen Williams
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  This program is free software; you can redistribute it and/or modify
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  it under the terms of the GNU General Public License as published by
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  the Free Software Foundation; either version 2 of the License, or
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  (at your option) any later version.
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  This program is distributed in the hope that it will be useful,
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  but WITHOUT ANY WARRANTY; without even the implied warranty of
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  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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  GNU General Public License for more details.
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  You should have received a copy of the GNU General Public License along
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  with this program; if not, write to the Free Software Foundation, Inc.,
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  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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translate: /usr/lib/ivl/ivlpp  -v -L -F"/tmp/ivrlg238274735" -f"/tmp/ivrlg38274735" -p"/tmp/ivrli38274735"  | /usr/lib/ivl/ivl -v -C"/tmp/ivrlh38274735" -C"/usr/lib/ivl/vvp.conf" -- -

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