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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MESI_ISC Project                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Yair Amitay       yair.amitay@yahoo.com               ////
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////                          www.linkedin.com/in/yairamitay      ////
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////                                                              ////
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////  Description                                                 ////
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////  mesi_isc                                                    ////
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////  -------------------                                         ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "mesi_isc_define.v"
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module mesi_isc
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    (
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     // Inputs
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     clk,
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     rst,
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     mbus_cmd3_i,
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     mbus_cmd2_i,
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     mbus_cmd1_i,
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     mbus_cmd0_i,
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     mbus_addr3_i,
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     mbus_addr2_i,
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     mbus_addr1_i,
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     mbus_addr0_i,
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     cbus_ack3_i,
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     cbus_ack2_i,
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     cbus_ack1_i,
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     cbus_ack0_i,
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     // Outputs
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     cbus_addr_o,
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     cbus_cmd3_o,
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     cbus_cmd2_o,
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     cbus_cmd1_o,
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     cbus_cmd0_o,
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     mbus_ack3_o,
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     mbus_ack2_o,
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     mbus_ack1_o,
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     mbus_ack0_o
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   );
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parameter
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  CBUS_CMD_WIDTH           = 3,
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  ADDR_WIDTH               = 32,
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  BROAD_TYPE_WIDTH         = 2,
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  BROAD_ID_WIDTH           = 5,
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  BROAD_REQ_FIFO_SIZE      = 4,
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  BROAD_REQ_FIFO_SIZE_LOG2 = 2,
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  MBUS_CMD_WIDTH           = 3,
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  BREQ_FIFO_SIZE           = 2,
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  BREQ_FIFO_SIZE_LOG2      = 1;
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// Inputs
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//================================
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// System
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input                   clk;          // System clock
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input                   rst;          // Active high system reset
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// Main buses
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input [MBUS_CMD_WIDTH-1:0] mbus_cmd3_i; // Main bus3 command
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input [MBUS_CMD_WIDTH-1:0] mbus_cmd2_i; // Main bus2 command
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input [MBUS_CMD_WIDTH-1:0] mbus_cmd1_i; // Main bus1 command
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input [MBUS_CMD_WIDTH-1:0] mbus_cmd0_i; // Main bus0 command
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// Coherence buses
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input [ADDR_WIDTH-1:0]  mbus_addr3_i;  // Coherence bus3 address
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input [ADDR_WIDTH-1:0]  mbus_addr2_i;  // Coherence bus2 address
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input [ADDR_WIDTH-1:0]  mbus_addr1_i;  // Coherence bus1 address
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input [ADDR_WIDTH-1:0]  mbus_addr0_i;  // Coherence bus0 address
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input                   cbus_ack3_i;  // Coherence bus3 acknowledge
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input                   cbus_ack2_i;  // Coherence bus2 acknowledge
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input                   cbus_ack1_i;  // Coherence bus1 acknowledge
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input                   cbus_ack0_i;  // Coherence bus0 acknowledge
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// Outputs
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//================================
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output [ADDR_WIDTH-1:0] cbus_addr_o;  // Coherence bus address. All busses have
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                                      // the same address
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output [CBUS_CMD_WIDTH-1:0] cbus_cmd3_o; // Coherence bus3 command
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output [CBUS_CMD_WIDTH-1:0] cbus_cmd2_o; // Coherence bus2 command
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output [CBUS_CMD_WIDTH-1:0] cbus_cmd1_o; // Coherence bus1 command
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output [CBUS_CMD_WIDTH-1:0] cbus_cmd0_o; // Coherence bus0 command
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output                  mbus_ack3_o;  // Main bus3 acknowledge
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output                  mbus_ack2_o;  // Main bus2 acknowledge
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output                  mbus_ack1_o;  // Main bus1 acknowledge
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output                  mbus_ack0_o;  // Main bus0 acknowledge
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// Regs & wires
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//================================
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wire                    broad_fifo_wr;
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wire [ADDR_WIDTH-1:0]   broad_addr;
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wire [BROAD_ID_WIDTH-1:0] broad_id;
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wire [BROAD_TYPE_WIDTH-1:0] broad_type;
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wire [1:0]              broad_cpu_id;
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wire                    broad_fifo_status_full;
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// mesi_isc_broad
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//================================
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mesi_isc_broad #(CBUS_CMD_WIDTH,
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                 ADDR_WIDTH,
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                 BROAD_TYPE_WIDTH,
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                 BROAD_ID_WIDTH,
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                 BROAD_REQ_FIFO_SIZE,
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                 BROAD_REQ_FIFO_SIZE_LOG2)
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  mesi_isc_broad
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    (
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     // Inputs
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     .clk                      (clk),
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     .rst                      (rst),
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     .cbus_ack_array_i         ({cbus_ack3_i,
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                                 cbus_ack2_i,
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                                 cbus_ack1_i,
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                                 cbus_ack0_i}
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                               ),
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     .broad_fifo_wr_i          (broad_fifo_wr  ),
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     .broad_addr_i             (broad_addr[ADDR_WIDTH-1:0]),
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     .broad_type_i             (broad_type[BROAD_TYPE_WIDTH-1:0]),
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     .broad_cpu_id_i           (broad_cpu_id[1:0]),
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     .broad_id_i               (broad_id[BROAD_ID_WIDTH-1:0]),
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     // Outputs
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     .cbus_addr_o              (cbus_addr_o[ADDR_WIDTH-1:0]),
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     .cbus_cmd_array_o         ({cbus_cmd3_o[CBUS_CMD_WIDTH-1:0],
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                                 cbus_cmd2_o[CBUS_CMD_WIDTH-1:0],
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                                 cbus_cmd1_o[CBUS_CMD_WIDTH-1:0],
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                                 cbus_cmd0_o[CBUS_CMD_WIDTH-1:0]}
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                               ),
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     .fifo_status_full_o       (broad_fifo_status_full)
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     );
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// mesi_isc_breq_fifos
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//================================
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mesi_isc_breq_fifos #(MBUS_CMD_WIDTH,
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                      ADDR_WIDTH,
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                      BROAD_TYPE_WIDTH,
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                      BROAD_ID_WIDTH,
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                      BREQ_FIFO_SIZE,
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                      BREQ_FIFO_SIZE_LOG2)
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  mesi_isc_breq_fifos
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    (
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     // Inputs
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     .clk                      (clk),
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     .rst                      (rst),
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     .mbus_cmd_array_i         ({mbus_cmd3_i[MBUS_CMD_WIDTH-1:0],
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                                 mbus_cmd2_i[MBUS_CMD_WIDTH-1:0],
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                                 mbus_cmd1_i[MBUS_CMD_WIDTH-1:0],
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                                 mbus_cmd0_i[MBUS_CMD_WIDTH-1:0]}
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                               ),
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     .mbus_addr_array_i        ({mbus_addr3_i[ADDR_WIDTH-1:0],
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                                 mbus_addr2_i[ADDR_WIDTH-1:0],
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                                 mbus_addr1_i[ADDR_WIDTH-1:0],
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                                 mbus_addr0_i[ADDR_WIDTH-1:0]}
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                               ),
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     .broad_fifo_status_full_i (broad_fifo_status_full),
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     // Outputs
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     .mbus_ack_array_o         ({mbus_ack3_o,
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                                 mbus_ack2_o,
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                                 mbus_ack1_o,
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                                 mbus_ack0_o}
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                                ),
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     .broad_fifo_wr_o          (broad_fifo_wr  ),
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     .broad_addr_o             (broad_addr[ADDR_WIDTH-1:0]),
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     .broad_type_o             (broad_type[BROAD_TYPE_WIDTH-1:0]),
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     .broad_cpu_id_o           (broad_cpu_id[1:0]),
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     .broad_id_o               (broad_id[BROAD_ID_WIDTH-1:0])
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     );
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endmodule

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