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[/] [mesi_isc/] [trunk/] [src/] [rtl/] [mesi_isc_basic_fifo.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MESI_ISC Project                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Yair Amitay       yair.amitay@yahoo.com               ////
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////                          www.linkedin.com/in/yairamitay      ////
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////                                                              ////
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////  Description                                                 ////
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////  mesi_isc_basic_fifo                                         ////
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////  -------------------                                         ////
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////  The basic fifo is a fifo for instantiation in the different ////
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////  parts of the block                                          ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "mesi_isc_define.v"
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module mesi_isc_basic_fifo
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    (
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     // Inputs
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     clk,
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     rst,
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     wr_i,
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     rd_i,
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     data_i,
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     // Outputs
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     data_o,
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     status_empty_o,
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     status_full_o
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     );
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parameter
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  DATA_WIDTH        = 32,
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  FIFO_SIZE         = 4,
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  FIFO_SIZE_LOG2    = 2;
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// Inputs
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//================================
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// System
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input                   clk;          // System clock
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input                   rst;          // Active high system reset
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input                   wr_i;         // Write data to the fifo (store the data)
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input                   rd_i;         // Read data from the fifo. Data is erased
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                                      // afterward.
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input [DATA_WIDTH-1:0]  data_i;       // Data data in to be stored
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// Outputs
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//================================
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output [DATA_WIDTH-1:0] data_o;       // Data out to be rad 
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// Status outputs
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output                  status_empty_o; // There are no valid entries in the
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                                       // fifo
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output                  status_full_o; // There are no free entries in the fifo
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                                       //  all the entries are valid
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// Regs
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//================================
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reg  [DATA_WIDTH-1:0]   data_o;       // Data out to be rad 
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reg  [DATA_WIDTH-1:0]   entry [FIFO_SIZE-1:0];  // The fifo entries
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reg  [FIFO_SIZE_LOG2-1:0] ptr_wr;      // Fifo write pointer
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reg  [FIFO_SIZE_LOG2-1:0] ptr_rd;      // Fifo read pointer
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wire [FIFO_SIZE_LOG2-1:0] ptr_rd_plus_1;
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reg                     status_empty;
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reg                     status_full;
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wire [FIFO_SIZE_LOG2-1:0] fifo_depth;  // Number of used entries
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wire                    fifo_depth_increase;
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wire                    fifo_depth_decrease;
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integer                 i;             // For loop
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`ifdef mesi_isc_debug
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reg dbg_fifo_overflow;                 // Sticky bit for fifo overflow
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reg dbg_fifo_underflow;                // Sticky bit for fifo underflow
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`endif
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// Write to the fifo
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//================================
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// ptr_wr
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// entry array
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always @(posedge clk or posedge rst)
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  if (rst)
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  begin
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     for(i=0; i < FIFO_SIZE; i = i + 1 )
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       entry[i]    <= 0;
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     ptr_wr        <= 0;
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  end
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  else if (wr_i)
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  begin
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     entry[ptr_wr] <= data_i;        // Store the data_i to entry ptr_wr
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     ptr_wr[FIFO_SIZE_LOG2-1:0] <= ptr_wr[FIFO_SIZE_LOG2-1:0] + 1; // Increase
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                                     // the write pointer
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  end
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// Read from the fifo
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//================================
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// data_o
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// The fifo output data_o is sampled. It always contains the data of 
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// the entry[ptr_rd]; 
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always @(posedge clk or posedge rst)
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  if (rst)
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    data_o[DATA_WIDTH-1:0] <= 0;
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  else if (status_empty)
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    data_o[DATA_WIDTH-1:0] <= data_i[DATA_WIDTH-1:0]; // When the fifo is empty
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                                       // the write data
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                                       // (if exists) is sampled to the fifo and
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                                       // to the fifo output. In a case that in
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                                       // the current cycle there is a write and
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                                       // in the next cycle there is a read, the
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                                       // data is ready in the output
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  else if (rd_i)
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    data_o[DATA_WIDTH-1:0] <= entry[ptr_rd_plus_1]; // Output the next data if this
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                                       //  is a read cycle.
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  else
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    data_o[DATA_WIDTH-1:0] <= entry[ptr_rd]; // The first data is sampled and
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                                       //  ready for a read
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// ptr_rd
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always @(posedge clk or posedge rst)
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  if (rst)
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    ptr_rd[FIFO_SIZE_LOG2-1:0] <= 0;
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  else if (rd_i)
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    ptr_rd[FIFO_SIZE_LOG2-1:0] <= ptr_rd[FIFO_SIZE_LOG2-1:0] + 1; // Increase the
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                                       //  read pointer
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assign ptr_rd_plus_1 = ptr_rd + 1;
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// Status
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//================================
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assign  status_empty_o        = status_empty;
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assign  status_full_o         = status_full;
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// status_empty
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// status_empty is set when there are no any valid entries
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always @(posedge clk or posedge rst)
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  // On reset the fifo is empty
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  if (rst)
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                                                    status_empty <= 1;
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  // There is one valid entry which is read (without write another entry)
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  else if (fifo_depth == 1 & fifo_depth_decrease)
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                                                    status_empty <= 1;
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  // The fifo is empty and it is in a write cycle (without read)
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  // The fifo_depth == 0 when the fifo is empty and when it is full
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  else if (fifo_depth == 0   &
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           status_empty      &
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           fifo_depth_increase)
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                                                    status_empty <= 0;
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always @(posedge clk or posedge rst)
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  // On reset the fifo not full
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  if (rst)
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                                                    status_full  <= 0;
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  // There is free entry which is written (without read other entry)
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  else if (fifo_depth == FIFO_SIZE-1 & fifo_depth_increase)
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                                                    status_full  <= 1;
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  // The fifo is full and it is in a read cycle (without write)
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  // The fifo_depth == 0 when the fifo is empty and when it is full
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  else if (fifo_depth == 0 &
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           status_full     &
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           fifo_depth_decrease)
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                                                    status_full  <= 0;
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// The depth of the used fifo's entries is increased when there is a write
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// and there is no a read
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assign fifo_depth_increase     = wr_i & !rd_i;
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// The depth of the used fifo's entries is decreased when there is a write
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// and there is no a read
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assign fifo_depth_decrease     = !wr_i & rd_i;
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// In other cases (ptr_wr & ptr_rd) or (!ptr_wr & !ptr_rd) the number of the
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// valid entries remains the same
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// Because the buffer is cyclic the depth is always correct
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assign fifo_depth[FIFO_SIZE_LOG2-1:0] = ptr_wr[FIFO_SIZE_LOG2-1:0] -
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                                        ptr_rd[FIFO_SIZE_LOG2-1:0];
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`ifdef mesi_isc_debug
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// Debug
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//================================
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// dbg_fifo_overflow is a sticky bit which is set when writing (without reading)
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// to a full fifo
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// dbg_fifo_underflow is a sticky bit which is set when reading from an empty
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// fifo
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always @(posedge clk or posedge rst)
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  if (rst)
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    begin
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     dbg_fifo_overflow   <= 0;
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     dbg_fifo_underflow  <= 0;
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    end
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  else
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  begin
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     dbg_fifo_overflow   <= dbg_fifo_overflow |
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                            (status_full & fifo_depth_increase);
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     dbg_fifo_underflow  <= dbg_fifo_underflow  |
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                            (status_empty & fifo_depth_decrease);
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  end
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`endif
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endmodule
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