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[/] [mesi_isc/] [trunk/] [src/] [rtl/] [mesi_isc_breq_fifos.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MESI_ISC Project                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Yair Amitay       yair.amitay@yahoo.com               ////
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////                          www.linkedin.com/in/yairamitay      ////
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////                                                              ////
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////  Description                                                 ////
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////  mesi_isc_breq_fifos                                         ////
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////  -------------------                                         ////
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////  Stores all the snoop transactions. Keeps the transactions   ////
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////  until the cpu receives the transactions                     ////
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////                                                              ////
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////  The functional ports of the block are arranged in arrays.   ////
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////  Each functional port is an array which contains one signal  ////
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////  for each snoop fifo.                                        ////
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////  The order of the signals, of width X (each signal has       //// 
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////  X-1:0 bits), in the port is described below.                ////
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////  All the bits of the first signal are located in the port    ////
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////  least significant bits. Then, the second signal is located  ////
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////  in the next X bits, etc.                                    ////
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////                                                              ////
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////  For a port that contains M (M>1) signals of width X (X>0)   ////
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////  signal_N[X-1:0] = port[(N+1)*X-1:N*X].                      ////
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////                                                              ////
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////  For example for a port with 4 signals of 8 bits             ////
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////  signal_0[7:0] = port[(N+1)*X-1:N*X] = port[(N+1)*8-1:N*8] = ////
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////                = port[(0+1)*8-1:0*8] = port[7:0]             ////
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////  signal_1[7:0] = port[(1+1)*8-1:1*8] = port[15:8]            ////
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////  signal_2[7:0] = port[(2+1)*8-1:2*8] = port[23:16]           ////
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////  signal_3[7:0] = port[(3+1)*8-1:3*8] = port[31:24]           ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "mesi_isc_define.v"
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module mesi_isc_breq_fifos
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    (
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     // Inputs
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     clk,
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     rst,
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     mbus_cmd_array_i,
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     mbus_addr_array_i,
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     broad_fifo_status_full_i,
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     // Outputs
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     mbus_ack_array_o,
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     broad_fifo_wr_o,
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     broad_addr_o,
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     broad_type_o,
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     broad_cpu_id_o,
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     broad_id_o
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   );
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85
parameter
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  MBUS_CMD_WIDTH           = 3,
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  ADDR_WIDTH               = 32,
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  BROAD_TYPE_WIDTH         = 2,
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  BROAD_ID_WIDTH           = 7,
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  BREQ_FIFO_SIZE           = 2,
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  BREQ_FIFO_SIZE_LOG2      = 1;
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// Inputs
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//================================
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// System
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input                   clk;          // System clock
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input                   rst;          // Active high system reset
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// Main buses
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input [4*MBUS_CMD_WIDTH-1:0] mbus_cmd_array_i; // Main bus command (array)
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input [4*ADDR_WIDTH-1:0] mbus_addr_array_i; // Main bus address (array)
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// From mesi_isc_broad_fifo
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input                    broad_fifo_status_full_i; // The broad fifo is full
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                                      // and can't receive another broadcast
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                                      // request
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// Outputs
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//================================
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// Main buses
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output [3:0]             mbus_ack_array_o; // Bus acknowledge for receiving the
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                                      // broadcast request
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// To mesi_isc_broad_fifo
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output                   broad_fifo_wr_o; // Write the broadcast request
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output [ADDR_WIDTH-1:0]  broad_addr_o; // Address of the broadcast request
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output [BROAD_TYPE_WIDTH-1:0] broad_type_o; // Type of the broadcast request
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output [1:0]             broad_cpu_id_o; // ID of the initiator CPU
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                                      // broad in the broad fifo
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output [BROAD_ID_WIDTH-1:0] broad_id_o; // The ID of the broadcast request
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// Regs & wires
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//================================
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wire [3:0]               fifo_status_empty_array;
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wire [3:0]              fifo_status_full_array;
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wire [4*ADDR_WIDTH-1:0] broad_addr_array;
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wire [4*BROAD_TYPE_WIDTH-1:0] broad_type_array;
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wire [4*BROAD_ID_WIDTH-1:0] broad_id_array;
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wire [3:0]               fifo_wr_array;
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wire [3:0]               fifo_rd_array;
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wire [4*BROAD_TYPE_WIDTH-1:0] breq_type_array;
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wire [4*2-1:0]          breq_cpu_id_array;
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wire [4*BROAD_ID_WIDTH-1:0] breq_id_array;
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wire [4*2-1:0]               broad_cpu_id_array;
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// Breq fifo control
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//================================
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mesi_isc_breq_fifos_cntl #(MBUS_CMD_WIDTH,
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                           ADDR_WIDTH,
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                           BROAD_TYPE_WIDTH,
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                           BROAD_ID_WIDTH)
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   mesi_isc_breq_fifos_cntl
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    (
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     // Inputs
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     .clk                   (clk),
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     .rst                   (rst),
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     .mbus_cmd_array_i      (mbus_cmd_array_i [4*MBUS_CMD_WIDTH-1     :0]),
148
     .fifo_status_empty_array_i (fifo_status_empty_array            [3:0]),
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     .fifo_status_full_array_i  (fifo_status_full_array             [3:0]),
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     .broad_fifo_status_full_i (broad_fifo_status_full_i),
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     .broad_addr_array_i    (broad_addr_array  [4*ADDR_WIDTH-1        :0]),
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     .broad_type_array_i    (broad_type_array  [4*BROAD_TYPE_WIDTH-1  :0]),
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     .broad_id_array_i      (broad_id_array    [4*BROAD_ID_WIDTH-1    :0]),
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     // Outputs
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     .mbus_ack_array_o      (mbus_ack_array_o                        [3:0]),
156
     .fifo_wr_array_o       (fifo_wr_array                          [3:0]),
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     .fifo_rd_array_o       (fifo_rd_array                          [3:0]),
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     .broad_fifo_wr_o       (broad_fifo_wr_o),
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     .broad_addr_o          (broad_addr_o      [ADDR_WIDTH-1          :0]),
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     .broad_type_o          (broad_type_o      [BROAD_TYPE_WIDTH-1    :0]),
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     .broad_cpu_id_o        (broad_cpu_id_o                         [1:0]),
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     .broad_id_o            (broad_id_o        [BROAD_ID_WIDTH-1      :0]),
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     .breq_type_array_o     (breq_type_array   [4*BROAD_TYPE_WIDTH-1  :0]),
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     .breq_cpu_id_array_o   (breq_cpu_id_array [4*2-1                 :0]),
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     .breq_id_array_o       (breq_id_array     [4*BROAD_ID_WIDTH-1    :0])
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     );
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168
// Breq fifo 3
169
//================================
170
mesi_isc_basic_fifo #(ADDR_WIDTH         +  // DATA_WIDTH
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                      BROAD_TYPE_WIDTH   +
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                      2                  +  // BROAD_CPU_ID_WIDTH
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                      BROAD_ID_WIDTH,
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                      BREQ_FIFO_SIZE,       // FIFO_SIZE
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                      BREQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
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   //  \ /  (\ / marks the fifo ID) 
177
   fifo_3
178
    (
179
     // Inputs
180
     .clk                   (clk),
181
     .rst                   (rst),
182
                            //            \ /
183
     .wr_i                  (fifo_wr_array[3]),
184
                            //            \ /
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     .rd_i                  (fifo_rd_array[3]),
186
                            //                 \ /
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     .data_i                ({mbus_addr_array_i[(3+1)*ADDR_WIDTH-1:
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                            //                          \ /
189
                                                         3*ADDR_WIDTH],
190
                            //                 \ /
191
                              breq_type_array [(3+1)*BROAD_TYPE_WIDTH-1:
192
                            //                          \ /
193
                                                         3*BROAD_TYPE_WIDTH],
194
                            //                  \ /
195
                              breq_cpu_id_array[(3+1)*2-1:
196
                            //                          \ /
197
                                                         3*2],
198
                            //                 \ /
199
                              breq_id_array   [(3+1)*BROAD_ID_WIDTH-1:
200
                            //                          \ /
201
                                                         3*BROAD_ID_WIDTH]}),
202
     // Outputs
203
     //                     //                 \ /
204
     .data_o                ({broad_addr_array [(3+1)*ADDR_WIDTH-1:
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                            //                          \ /
206
                                                         3*ADDR_WIDTH],
207
                            //                 \ /
208
                             broad_type_array  [(3+1)*BROAD_TYPE_WIDTH-1:
209
                            //                          \ /
210
                                                         3*BROAD_TYPE_WIDTH],
211
                            //                  \ /
212
                             broad_cpu_id_array[(3+1)*2-1:
213
                            //                          \ /
214
                                                         3*2],
215
                            //                 \ /
216
                             broad_id_array    [(3+1)*BROAD_ID_WIDTH-1:
217
                            //                          \ /
218
                                                         3*BROAD_ID_WIDTH]}),
219
                            //                             \ /
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     .status_empty_o        (fifo_status_empty_array       [3]),
221
                            //                             \ /
222
     .status_full_o         (fifo_status_full_array        [3])
223
     );
224
 
225
// Breq fifo 2
226
//================================
227
mesi_isc_basic_fifo #(ADDR_WIDTH         +  // DATA_WIDTH
228
                      BROAD_TYPE_WIDTH   +
229
                      2                  +  // BROAD_CPU_ID_WIDTH
230
                      BROAD_ID_WIDTH,
231
                      BREQ_FIFO_SIZE,       // FIFO_SIZE
232
                      BREQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
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   //  \ /  (\ / marks the fifo ID) 
234
   fifo_2
235
    (
236
     // Inputs
237
     .clk                   (clk),
238
     .rst                   (rst),
239
                            //            \ /
240
     .wr_i                  (fifo_wr_array[2]),
241
                            //            \ /
242
     .rd_i                  (fifo_rd_array[2]),
243
                            //                 \ /
244
     .data_i                ({mbus_addr_array_i[(2+1)*ADDR_WIDTH-1:
245
                            //                          \ /
246
                                                         2*ADDR_WIDTH],
247
                            //                 \ /
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                              breq_type_array [(2+1)*BROAD_TYPE_WIDTH-1:
249
                            //                          \ /
250
                                                         2*BROAD_TYPE_WIDTH],
251
                            //                  \ /
252
                              breq_cpu_id_array[(2+1)*2-1:
253
                            //                          \ /
254
                                                         2*2],
255
                            //                 \ /
256
                              breq_id_array   [(2+1)*BROAD_ID_WIDTH-1:
257
                            //                          \ /
258
                                                         2*BROAD_ID_WIDTH]}),
259
     // Outputs
260
     //                     //                 \ /
261
     .data_o                ({broad_addr_array [(2+1)*ADDR_WIDTH-1:
262
                            //                          \ /
263
                                                         2*ADDR_WIDTH],
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                            //                 \ /
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                             broad_type_array  [(2+1)*BROAD_TYPE_WIDTH-1:
266
                            //                          \ /
267
                                                         2*BROAD_TYPE_WIDTH],
268
                            //                  \ /
269
                             broad_cpu_id_array[(2+1)*2-1:
270
                            //                          \ /
271
                                                         2*2],
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                            //                 \ /
273
                             broad_id_array    [(2+1)*BROAD_ID_WIDTH-1:
274
                            //                          \ /
275
                                                         2*BROAD_ID_WIDTH]}),
276
                            //                             \ /
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     .status_empty_o        (fifo_status_empty_array       [2]),
278
                            //                             \ /
279
     .status_full_o         (fifo_status_full_array        [2])
280
     );
281
 
282
// Breq fifo 1
283
//================================
284
mesi_isc_basic_fifo #(ADDR_WIDTH         +  // DATA_WIDTH
285
                      BROAD_TYPE_WIDTH   +
286
                      2                  +  // BROAD_CPU_ID_WIDTH
287
                      BROAD_ID_WIDTH,
288
                      BREQ_FIFO_SIZE,       // FIFO_SIZE
289
                      BREQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
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   //  \ /  (\ / marks the fifo ID) 
291
   fifo_1
292
    (
293
     // Inputs
294
     .clk                   (clk),
295
     .rst                   (rst),
296
                            //            \ /
297
     .wr_i                  (fifo_wr_array[1]),
298
                            //            \ /
299
     .rd_i                  (fifo_rd_array[1]),
300
                            //                 \ /
301
     .data_i                ({mbus_addr_array_i[(1+1)*ADDR_WIDTH-1:
302
                            //                          \ /
303
                                                         1*ADDR_WIDTH],
304
                            //                 \ /
305
                              breq_type_array [(1+1)*BROAD_TYPE_WIDTH-1:
306
                            //                          \ /
307
                                                         1*BROAD_TYPE_WIDTH],
308
                            //                  \ /
309
                              breq_cpu_id_array[(1+1)*2-1:
310
                            //                          \ /
311
                                                         1*2],
312
                            //                 \ /
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                              breq_id_array   [(1+1)*BROAD_ID_WIDTH-1:
314
                            //                          \ /
315
                                                         1*BROAD_ID_WIDTH]}),
316
     // Outputs
317
     //                     //                 \ /
318
     .data_o                ({broad_addr_array [(1+1)*ADDR_WIDTH-1:
319
                            //                          \ /
320
                                                         1*ADDR_WIDTH],
321
                            //                 \ /
322
                             broad_type_array  [(1+1)*BROAD_TYPE_WIDTH-1:
323
                            //                          \ /
324
                                                         1*BROAD_TYPE_WIDTH],
325
                            //                  \ /
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                             broad_cpu_id_array[(1+1)*2-1:
327
                            //                          \ /
328
                                                         1*2],
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                            //                 \ /
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                             broad_id_array    [(1+1)*BROAD_ID_WIDTH-1:
331
                            //                          \ /
332
                                                         1*BROAD_ID_WIDTH]}),
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                            //                             \ /
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     .status_empty_o        (fifo_status_empty_array       [1]),
335
                            //                             \ /
336
     .status_full_o         (fifo_status_full_array        [1])
337
     );
338
 
339
// Breq fifo 0
340
//================================
341
mesi_isc_basic_fifo #(ADDR_WIDTH         +  // DATA_WIDTH
342
                      BROAD_TYPE_WIDTH   +
343
                      2                  +  // BROAD_CPU_ID_WIDTH
344
                      BROAD_ID_WIDTH,
345
                      BREQ_FIFO_SIZE,       // FIFO_SIZE
346
                      BREQ_FIFO_SIZE_LOG2)  // FIFO_SIZE_LOG2
347
   //  \ /  (\ / marks the fifo ID) 
348
   fifo_0
349
    (
350
     // Inputs
351
     .clk                   (clk),
352
     .rst                   (rst),
353
                            //            \ /
354
     .wr_i                  (fifo_wr_array[0]),
355
                            //            \ /
356
     .rd_i                  (fifo_rd_array[0]),
357
                            //                 \ /
358
     .data_i                ({mbus_addr_array_i[(0+1)*ADDR_WIDTH-1:
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                            //                          \ /
360
                                                         0*ADDR_WIDTH],
361
                            //                 \ /
362
                              breq_type_array [(0+1)*BROAD_TYPE_WIDTH-1:
363
                            //                          \ /
364
                                                         0*BROAD_TYPE_WIDTH],
365
                            //                  \ /
366
                              breq_cpu_id_array[(0+1)*2-1:
367
                            //                          \ /
368
                                                         0*2],
369
                            //                 \ /
370
                              breq_id_array   [(0+1)*BROAD_ID_WIDTH-1:
371
                            //                          \ /
372
                                                         0*BROAD_ID_WIDTH]}),
373
     // Outputs
374
     //                     //                 \ /
375
     .data_o                ({broad_addr_array [(0+1)*ADDR_WIDTH-1:
376
                            //                          \ /
377
                                                         0*ADDR_WIDTH],
378
                            //                 \ /
379
                             broad_type_array  [(0+1)*BROAD_TYPE_WIDTH-1:
380
                            //                          \ /
381
                                                         0*BROAD_TYPE_WIDTH],
382
                            //                  \ /
383
                             broad_cpu_id_array[(0+1)*2-1:
384
                            //                          \ /
385
                                                         0*2],
386
                            //                 \ /
387
                             broad_id_array    [(0+1)*BROAD_ID_WIDTH-1:
388
                            //                          \ /
389
                                                         0*BROAD_ID_WIDTH]}),
390
                            //                             \ /
391
     .status_empty_o        (fifo_status_empty_array       [0]),
392
                            //                             \ /
393
     .status_full_o         (fifo_status_full_array        [0])
394
     );
395
 
396
endmodule

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