OpenCores
URL https://opencores.org/ocsvn/mesi_isc/mesi_isc/trunk

Subversion Repositories mesi_isc

[/] [mesi_isc/] [trunk/] [src/] [rtl/] [mesi_isc_define.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 yaira
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
//////////////////////////////////////////////////////////////////////
29
////                                                              ////
30
////  MESI_ISC Project                                            ////
31
////                                                              ////
32
////  Author(s):                                                  ////
33
////      - Yair Amitay       yair.amitay@yahoo.com               ////
34
////                          www.linkedin.com/in/yairamitay      ////
35
////                                                              ////
36
////  Description                                                 ////
37
////  mesi_isc_define                                             ////
38
////  -------------------                                         ////
39
////  Contains the timescale and the define declaration of the    ////
40
////  block                                                       ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
`timescale 1ns / 1ps
44
 
45
// Main Bus commands
46
`define MESI_ISC_MBUS_CMD_NOP      3'd0
47
`define MESI_ISC_MBUS_CMD_WR       3'd1
48
`define MESI_ISC_MBUS_CMD_RD       3'd2
49
`define MESI_ISC_MBUS_CMD_WR_BROAD 3'd3
50
`define MESI_ISC_MBUS_CMD_RD_BROAD 3'd4
51
 
52
// Coherence Bus commands
53
`define MESI_ISC_CBUS_CMD_NOP      3'd0
54
`define MESI_ISC_CBUS_CMD_WR_SNOOP 3'd1
55
`define MESI_ISC_CBUS_CMD_RD_SNOOP 3'd2
56
`define MESI_ISC_CBUS_CMD_EN_WR    3'd3
57
`define MESI_ISC_CBUS_CMD_EN_RD    3'd4
58
 
59
// BREQ_TYPE  
60
`define MESI_ISC_BREQ_TYPE_NOP 2'd0
61
`define MESI_ISC_BREQ_TYPE_WR  2'd1
62
`define MESI_ISC_BREQ_TYPE_RD  2'd2
63
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.