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//////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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28
//////////////////////////////////////////////////////////////////////
29
////                                                              ////
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////  MESI_ISC Project                                            ////
31
////                                                              ////
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////  Author(s):                                                  ////
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////      - Yair Amitay       yair.amitay@yahoo.com               ////
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////                          www.linkedin.com/in/yairamitay      ////
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////                                                              ////
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////  Description                                                 ////
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////  mesi_isc_tb                                                 ////
38
////  -------------------                                         ////
39
////  Project test bench                                          ////
40
////  - Instantiation of the top level module mesi_isc            ////
41
////  - Generates the tests stimulus                              ////
42
////  - Simulate the CPU and caches                               ////
43
////  - Generates clock, reset and watchdog                       ////
44
////  - Generate statistic                                        ////
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////  - Generate dump file                                        ////
46
////  - Check for behavior correctness                            ////
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////  - Check for coherency correctness                           ////
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////                                                              ////
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////  For more details see the project spec document.             ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
54
 
55
`include "mesi_isc_define.v"
56
`include "mesi_isc_tb_define.v"
57
 
58
module mesi_isc_tb
59
    (
60
     // Inputs
61
     // Outputs
62
     );
63
 
64
parameter
65
  CBUS_CMD_WIDTH           = 3,
66
  ADDR_WIDTH               = 32,
67
  DATA_WIDTH               = 32,
68
  BROAD_TYPE_WIDTH         = 2,
69
  BROAD_ID_WIDTH           = 5,
70
  BROAD_REQ_FIFO_SIZE      = 4,
71
  BROAD_REQ_FIFO_SIZE_LOG2 = 2,
72
  MBUS_CMD_WIDTH           = 3,
73
  BREQ_FIFO_SIZE           = 2,
74
  BREQ_FIFO_SIZE_LOG2      = 1;
75
 
76
/// Regs and wires
77
//================================
78
// System
79
reg                   clk;          // System clock
80
reg                   rst;          // Active high system reset
81
 
82
// Main buses
83
wire  [MBUS_CMD_WIDTH-1:0] mbus_cmd_array [3:0]; // Main bus3 command
84
wire  [MBUS_CMD_WIDTH-1:0] mbus_cmd3; // Main bus2 command
85
wire  [MBUS_CMD_WIDTH-1:0] mbus_cmd2; // Main bus2 command
86
wire  [MBUS_CMD_WIDTH-1:0] mbus_cmd1; // Main bus1 command
87
wire  [MBUS_CMD_WIDTH-1:0] mbus_cmd0; // Main bus0 command
88
// Coherence buses
89
wire  [ADDR_WIDTH-1:0]  mbus_addr_array [3:0];  // Main bus3 address
90
wire  [ADDR_WIDTH-1:0]  mbus_addr3;  // Main bus3 address
91
wire  [ADDR_WIDTH-1:0]  mbus_addr2;  // Main bus2 address
92
wire  [ADDR_WIDTH-1:0]  mbus_addr1;  // Main bus1 address
93
wire  [ADDR_WIDTH-1:0]  mbus_addr0;  // Main bus0 address
94
reg   [DATA_WIDTH-1:0]  mbus_data_rd;  // Main bus data read
95
wire  [DATA_WIDTH-1:0]  mbus_data_wr_array [3:0];  // Main bus data read
96
wire  [DATA_WIDTH-1:0]  mbus_data_wr3;  // Main bus data read
97
wire  [DATA_WIDTH-1:0]  mbus_data_wr2;  // Main bus data read
98
wire  [DATA_WIDTH-1:0]  mbus_data_wr1;  // Main bus data read
99
wire  [DATA_WIDTH-1:0]  mbus_data_wr0;  // Main bus data read
100
 
101
wire  [7:0]             mbus_data_rd_word_array [3:0]; // Bus data read in words
102
                                        // word
103
 
104
wire                    cbus_ack3;  // Coherence bus3 acknowledge
105
wire                    cbus_ack2;  // Coherence bus2 acknowledge
106
wire                    cbus_ack1;  // Coherence bus1 acknowledge
107
wire                    cbus_ack0;  // Coherence bus0 acknowledge
108
 
109
 
110
wire   [ADDR_WIDTH-1:0] cbus_addr;  // Coherence bus address. All busses have
111
                                      // the same address
112
wire   [CBUS_CMD_WIDTH-1:0] cbus_cmd3; // Coherence bus3 command
113
wire   [CBUS_CMD_WIDTH-1:0] cbus_cmd2; // Coherence bus2 command
114
wire   [CBUS_CMD_WIDTH-1:0] cbus_cmd1; // Coherence bus1 command
115
wire   [CBUS_CMD_WIDTH-1:0] cbus_cmd0; // Coherence bus0 command
116
 
117
wire   [3:0]            mbus_ack;  // Main bus3 acknowledge
118
reg    [3:0]            mbus_ack_memory;
119
wire   [3:0]            mbus_ack_mesi_isc;
120
reg    [3:0]            tb_ins_array [3:0];
121
wire   [3:0]            tb_ins3;
122
wire   [3:0]            tb_ins2;
123
wire   [3:0]            tb_ins1;
124
wire   [3:0]            tb_ins0;
125
reg    [3:0]            tb_ins_addr_array [3:0];
126
wire   [3:0]            tb_ins_addr3;
127
wire   [3:0]            tb_ins_addr2;
128
wire   [3:0]            tb_ins_addr1;
129
wire   [3:0]            tb_ins_addr0;
130
reg    [7:0]            tb_ins_nop_period [3:0];
131
wire   [7:0]            tb_ins_nop_period3;
132
wire   [7:0]            tb_ins_nop_period2;
133
wire   [7:0]            tb_ins_nop_period1;
134
wire   [7:0]            tb_ins_nop_period0;
135
wire   [3:0]            tb_ins_ack;
136
reg    [31:0]           mem   [9:0];  // Main memory
137
wire   [31:0]           mem0;
138
wire   [31:0]           mem1;
139
wire   [31:0]           mem2;
140
wire   [31:0]           mem3;
141
wire   [31:0]           mem4;
142
wire   [31:0]           mem5;
143
wire   [31:0]           mem6;
144
wire   [31:0]           mem7;
145
wire   [31:0]           mem8;
146
wire   [31:0]           mem9;
147
reg    [1:0]            cpu_priority;
148
reg    [3:0]            cpu_selected;
149
reg                     mem_access;
150
integer                 stimulus_rand_numb [9:0];
151
integer                 seed;
152
reg    [1:0]            stimulus_rand_cpu_select;
153
reg    [1:0]            stimulus_op;
154
reg    [7:0]            stimulus_addr;
155
reg    [7:0]            stimulus_nop_period;
156
integer                 cur_stimulus_cpu;
157
// For debug in GTKwave
158
wire   [ADDR_WIDTH+BROAD_TYPE_WIDTH+2+BROAD_ID_WIDTH:0] broad_fifo_entry0;
159
wire   [ADDR_WIDTH+BROAD_TYPE_WIDTH+2+BROAD_ID_WIDTH:0] broad_fifo_entry1;
160
wire   [ADDR_WIDTH+BROAD_TYPE_WIDTH+2+BROAD_ID_WIDTH:0] broad_fifo_entry2;
161
wire   [ADDR_WIDTH+BROAD_TYPE_WIDTH+2+BROAD_ID_WIDTH:0] broad_fifo_entry3;
162
 
163
wire   [5:0]            cache_state_valid_array [3:0];
164
 
165
integer                 i, j, k, l, m, n, p;
166
 
167
reg [31:0]              stat_cpu_access_nop [3:0];
168
reg [31:0]              stat_cpu_access_rd  [3:0];
169
reg [31:0]              stat_cpu_access_wr  [3:0];
170
 
171
 
172
`include "mesi_isc_tb_sanity_check.v"
173
 
174
// Stimulus
175
//================================
176
// The stimulus drives instruction to the CPU. There are three possible 
177
// instructions:
178
// 1. NOP - Do nothing for a random cycles.   
179
// 2. RD - Read a memory address line with a random address. If the line address
180
//    is valid on the cache read it from there, if not bring the line according
181
//    to the the MESI protocol.
182
// 3. WR - Write a memory address line with a random address. If the line address
183
//    is valid on the cache write to it according to the MESI protocol. If it is
184
//    not valid, bring it from the memory according to the the MESI protocol.
185
always @(posedge clk or posedge rst)
186
  if (rst)
187
  begin
188
   tb_ins_array[3]      = `MESI_ISC_TB_INS_NOP;
189
   tb_ins_array[2]      = `MESI_ISC_TB_INS_NOP;
190
   tb_ins_array[1]      = `MESI_ISC_TB_INS_NOP;
191
   tb_ins_array[0]      = `MESI_ISC_TB_INS_NOP;
192
   tb_ins_addr_array[3] = 0;
193
   tb_ins_addr_array[2] = 0;
194
   tb_ins_addr_array[1] = 0;
195
   tb_ins_addr_array[0] = 0;
196
   tb_ins_nop_period[3] = 0;
197
   tb_ins_nop_period[2] = 0;
198
   tb_ins_nop_period[1] = 0;
199
   tb_ins_nop_period[0] = 0;
200
  end
201
  else
202
  begin
203
    // Calculate the random numbers for this cycle. Use one $random command
204
    // to perform one series of random number depends on the seed.
205
    for (m = 0; m < 9; m = m + 1)
206
      stimulus_rand_numb[m] = $random(seed);
207
 
208
    // For the current cycle check all the CPU starting in a random CPU ID 
209
    stimulus_rand_cpu_select = $unsigned(stimulus_rand_numb[0]) % 4; // The
210
                                      // random CPU ID
211
    for (l = 0; l < 4; l = l + 1)
212
    begin
213
      // Start generate a request of CPU ID that equal to cur_stimulus_cpu
214
      cur_stimulus_cpu = (stimulus_rand_cpu_select+l) % 4;
215
      // This CPU is in NOP period
216
      // ----------------------------
217
      if(tb_ins_nop_period[cur_stimulus_cpu] > 0)
218
      begin
219
        tb_ins_array[cur_stimulus_cpu] = `MESI_ISC_TB_INS_NOP;
220
        // Decrease the counter by 1. When the counter value is 0 the NOP period
221
        // is finished
222
        tb_ins_nop_period[cur_stimulus_cpu] =
223
                                    tb_ins_nop_period[cur_stimulus_cpu] - 1;
224
      end
225
      // The CPU is return acknowledge for the last action. Change the 
226
      // instruction back to nop.
227
      // ----------------------------
228
     else if (tb_ins_ack[cur_stimulus_cpu])
229
        tb_ins_array[cur_stimulus_cpu] = `MESI_ISC_TB_INS_NOP;
230
      // Generate the next instruction for the CPU 
231
      // ----------------------------
232
      else if(tb_ins_array[cur_stimulus_cpu] == `MESI_ISC_TB_INS_NOP)
233
      begin
234
        // Decide the next operation - nop (0), wr (1), or rd (2)
235
        stimulus_op         = $unsigned(stimulus_rand_numb[1+l]) % 20 ;
236
        // Ratio: 1 - nop     1 - wr 5 - rd
237
        if (stimulus_op > 1) stimulus_op = 2;
238
        // Decide the next address operation 1 to 5
239
        stimulus_addr       = ($unsigned(stimulus_rand_numb[5+l]) % 5) + 1 ;
240
        // Decide the next  operation 1 to 10
241
        stimulus_nop_period = ($unsigned(stimulus_rand_numb[9]) % 10) + 1 ;
242
        // Next op is nop. Set the value of the counter
243
        if (stimulus_op == 0)
244
          tb_ins_nop_period[cur_stimulus_cpu] = stimulus_nop_period;
245
        else
246
        begin
247
          tb_ins_array[cur_stimulus_cpu] = stimulus_op; // 1 for wr, 2 for rd
248
          tb_ins_addr_array[cur_stimulus_cpu] = stimulus_addr;
249
        end
250
      end // if (tb_ins_array[cur_stimulus_cpu] == `MESI_ISC_TB_INS_NOP)
251
    end // for (l = 0; l < 4; l = l + 1)
252
 
253
  end // else: !if(rst)
254
 
255
// Statistic
256
//================================
257
always @(posedge clk or posedge rst)
258
if (rst)
259
  for (n = 0; n < 4; n = n + 1)
260
  begin
261
    stat_cpu_access_nop[n] = 0;
262
    stat_cpu_access_rd[n]  = 0;
263
    stat_cpu_access_wr[n]  = 0;
264
  end
265
else
266
  for (p = 0; p < 4; p = p + 1)
267
    if (tb_ins_ack[p])
268
      begin
269
      case (tb_ins_array[p])
270
        `MESI_ISC_TB_INS_NOP: stat_cpu_access_nop[p] = stat_cpu_access_nop[p]+1;
271
        `MESI_ISC_TB_INS_WR:  stat_cpu_access_wr[p]  = stat_cpu_access_wr[p] +1;
272
        `MESI_ISC_TB_INS_RD:  stat_cpu_access_rd[p]  = stat_cpu_access_rd[p] +1;
273
      endcase // case (tb_ins_array[p])
274
    end
275
 
276
// clock and reset
277
//================================
278
always #50
279
       clk = !clk;
280
 
281
// Reset and watchdog
282
//================================
283
initial
284
begin
285
  // Reset the memory
286
  for (j = 0; j < 10; j = j + 1)
287
    mem[j] = 0;
288
  clk = 1;
289
  rst = 1;
290
  repeat (10) @(negedge clk);
291
  rst = 0;
292
  repeat (20000) @(negedge clk);   // Watchdog
293
  $display ("Watchdog finish\n");
294
  $display ("Statistic\n");
295
  $display ("CPU 3. WR:%d RD:%d NOP:%d  \n", stat_cpu_access_wr[3],
296
                                            stat_cpu_access_rd[3],
297
                                            stat_cpu_access_nop[3]);
298
  $display ("CPU 2. WR:%d RD:%d NOP:%d\n", stat_cpu_access_wr[2],
299
                                            stat_cpu_access_rd[2],
300
                                            stat_cpu_access_nop[2]);
301
  $display ("CPU 1. WR:%d RD:%d NOP:%d\n", stat_cpu_access_wr[1],
302
                                            stat_cpu_access_rd[1],
303
                                            stat_cpu_access_nop[1]);
304
  $display ("CPU 0. WR: %d RD:%d NOP:%d\n", stat_cpu_access_wr[0],
305
                                            stat_cpu_access_rd[0],
306
                                            stat_cpu_access_nop[0]);
307
  $display ("Total rd and wr accesses: %d\n", stat_cpu_access_wr[3] +
308
                                              stat_cpu_access_rd[3] +
309
                                              stat_cpu_access_wr[2] +
310
                                              stat_cpu_access_rd[2] +
311
                                              stat_cpu_access_wr[1] +
312
                                              stat_cpu_access_rd[1] +
313
                                              stat_cpu_access_wr[0] +
314
                                              stat_cpu_access_rd[0]);
315
  $finish;
316
end
317
 
318
 
319
// Dumpfile
320
//================================
321
initial
322
begin
323
  $dumpfile("./dump.vcd");
324
  $dumpvars(0,mesi_isc_tb);
325
end
326
 
327
// Memory and matrix
328
//================================
329
always @(posedge clk or posedge rst)
330
  if (rst)
331
  begin
332
                     cpu_priority    = 0;
333
                     cpu_selected    = 0;
334
  end
335
  else
336
  begin
337
                     mbus_ack_memory = 0;
338
                     mem_access      = 0;
339
    for (i = 0; i < 4; i = i + 1)
340
       if ((mbus_cmd_array[cpu_priority+i] == `MESI_ISC_MBUS_CMD_WR |
341
            mbus_cmd_array[cpu_priority+i] == `MESI_ISC_MBUS_CMD_RD  ) &
342
            !mem_access)
343
    begin
344
                     mem_access      = 1;
345
                     cpu_selected    = cpu_priority+i;
346
                     mbus_ack_memory[cpu_priority+i] = 1;
347
      if (mbus_cmd_array[cpu_priority+i] == `MESI_ISC_MBUS_CMD_WR)
348
      // WR
349
      begin
350
                     sanity_check_rule1_rule2(cpu_selected,
351
                                            mbus_addr_array[cpu_priority+i],
352
                                            mbus_data_wr_array[cpu_priority+i]);
353
                     mem[mbus_addr_array[cpu_priority+i]] =
354
                                           mbus_data_wr_array[cpu_priority+i];
355
      end
356
      // RD
357
      else
358
                     mbus_data_rd =        mem[mbus_addr_array[cpu_priority+i]];
359
    end
360
  end
361
 
362
assign mbus_ack[3:0] = mbus_ack_memory[3:0] | mbus_ack_mesi_isc[3:0];
363
 
364
// Assigns
365
//================================
366
// GTKwave can't see arrays. points to array so GTKwave can see these signals
367
assign broad_fifo_entry0 = mesi_isc.mesi_isc_broad.broad_fifo.entry[0];
368
assign broad_fifo_entry1 = mesi_isc.mesi_isc_broad.broad_fifo.entry[1];
369
assign brroad_fifo_entry2 = mesi_isc.mesi_isc_broad.broad_fifo.entry[2];
370
assign brroad_fifo_entry3 = mesi_isc.mesi_isc_broad.broad_fifo.entry[3];
371
assign mbus_cmd3          = mbus_cmd_array[3];
372
assign mbus_cmd2          = mbus_cmd_array[2];
373
assign mbus_cmd1          = mbus_cmd_array[1];
374
assign mbus_cmd0          = mbus_cmd_array[0];
375
assign mbus_addr3         = mbus_addr_array[3];
376
assign mbus_addr2         = mbus_addr_array[2];
377
assign mbus_addr1         = mbus_addr_array[1];
378
assign mbus_addr0         = mbus_addr_array[0];
379
assign mbus_data_wr3      = mbus_data_wr_array[3];
380
assign mbus_data_wr2      = mbus_data_wr_array[2];
381
assign mbus_data_wr1      = mbus_data_wr_array[1];
382
assign mbus_data_wr0      = mbus_data_wr_array[0];
383
assign tb_ins3            = tb_ins_array[3];
384
assign tb_ins2            = tb_ins_array[2];
385
assign tb_ins1            = tb_ins_array[1];
386
assign tb_ins0            = tb_ins_array[0];
387
assign tb_ins_addr3       = tb_ins_addr_array[3];
388
assign tb_ins_addr2       = tb_ins_addr_array[2];
389
assign tb_ins_addr1       = tb_ins_addr_array[1];
390
assign tb_ins_addr0       = tb_ins_addr_array[0];
391
assign tb_ins_nop_period3 = tb_ins_nop_period[3];
392
assign tb_ins_nop_period2 = tb_ins_nop_period[2];
393
assign tb_ins_nop_period1 = tb_ins_nop_period[1];
394
assign tb_ins_nop_period0 = tb_ins_nop_period[0];
395
assign mem0 = mem[0];
396
assign mem1 = mem[1];
397
assign mem2 = mem[2];
398
assign mem3 = mem[3];
399
assign mem4 = mem[4];
400
assign mem5 = mem[5];
401
assign mem6 = mem[6];
402
assign mem7 = mem[7];
403
assign mem8 = mem[8];
404
assign mem9 = mem[9];
405
assign mbus_data_rd_word_array[3] = mbus_data_rd[31:24];
406
assign mbus_data_rd_word_array[2] = mbus_data_rd[23:16];
407
assign mbus_data_rd_word_array[1] = mbus_data_rd[15:8];
408
assign mbus_data_rd_word_array[0] = mbus_data_rd[7:0];
409
 
410
// Instantiations
411
//================================
412
 
413
 
414
// mesi_isc
415
mesi_isc #(CBUS_CMD_WIDTH,
416
           ADDR_WIDTH,
417
           BROAD_TYPE_WIDTH,
418
           BROAD_ID_WIDTH,
419
           BROAD_REQ_FIFO_SIZE,
420
           BROAD_REQ_FIFO_SIZE_LOG2,
421
           MBUS_CMD_WIDTH,
422
           BREQ_FIFO_SIZE,
423
           BREQ_FIFO_SIZE_LOG2
424
          )
425
  mesi_isc
426
    (
427
     // Inputs
428
     .clk              (clk),
429
     .rst              (rst),
430
     .mbus_cmd3_i      (mbus_cmd_array[3]),
431
     .mbus_cmd2_i      (mbus_cmd_array[2]),
432
     .mbus_cmd1_i      (mbus_cmd_array[1]),
433
     .mbus_cmd0_i      (mbus_cmd_array[0]),
434
     .mbus_addr3_i     (mbus_addr_array[3]),
435
     .mbus_addr2_i     (mbus_addr_array[2]),
436
     .mbus_addr1_i     (mbus_addr_array[1]),
437
     .mbus_addr0_i     (mbus_addr_array[0]),
438
     .cbus_ack3_i      (cbus_ack3),
439
     .cbus_ack2_i      (cbus_ack2),
440
     .cbus_ack1_i      (cbus_ack1),
441
     .cbus_ack0_i      (cbus_ack0),
442
     // Outputs
443
     .cbus_addr_o      (cbus_addr),
444
     .cbus_cmd3_o      (cbus_cmd3),
445
     .cbus_cmd2_o      (cbus_cmd2),
446
     .cbus_cmd1_o      (cbus_cmd1),
447
     .cbus_cmd0_o      (cbus_cmd0),
448
     .mbus_ack3_o      (mbus_ack_mesi_isc[3]),
449
     .mbus_ack2_o      (mbus_ack_mesi_isc[2]),
450
     .mbus_ack1_o      (mbus_ack_mesi_isc[1]),
451
     .mbus_ack0_o      (mbus_ack_mesi_isc[0])
452
    );
453
 
454
// mesi_isc_tb_cpu3
455
mesi_isc_tb_cpu  #(
456
       CBUS_CMD_WIDTH,
457
       ADDR_WIDTH,
458
       DATA_WIDTH,
459
       BROAD_TYPE_WIDTH,
460
       BROAD_ID_WIDTH,
461
       BROAD_REQ_FIFO_SIZE,
462
       BROAD_REQ_FIFO_SIZE_LOG2,
463
       MBUS_CMD_WIDTH,
464
       BREQ_FIFO_SIZE,
465
       BREQ_FIFO_SIZE_LOG2
466
      )
467
   //         \ /
468
   mesi_isc_tb_cpu3
469
    (
470
     // Inputs
471
     .clk              (clk),
472
     .rst              (rst),
473
     .cbus_addr_i      (cbus_addr),
474
     //                        \ /
475
     .cbus_cmd_i       (cbus_cmd3),
476
     //                             \ /
477
     .mbus_data_i      (mbus_data_rd),
478
     //                        \ /
479
     .mbus_ack_i       (mbus_ack[3]),
480
     //                   \ /
481
     .cpu_id_i         (2'd3),
482
     //                      \ /
483
     .tb_ins_i         (tb_ins_array[3]),
484
     //                           \ /
485
     .tb_ins_addr_i    (tb_ins_addr3),
486
     // Outputs                \ /
487
     .mbus_cmd_o       (mbus_cmd_array[3]),
488
      //                        \ /
489
     .mbus_addr_o      (mbus_addr_array[3]),
490
      //                        \ /
491
     .mbus_data_o      (mbus_data_wr_array[3]),
492
     //                        \ /
493
     .cbus_ack_o       (cbus_ack3),
494
     //                          \ /
495
     .tb_ins_ack_o     (tb_ins_ack[3])
496
 );
497
 
498
// mesi_isc_tb_cpu2
499
mesi_isc_tb_cpu  #(
500
       CBUS_CMD_WIDTH,
501
       ADDR_WIDTH,
502
       DATA_WIDTH,
503
       BROAD_TYPE_WIDTH,
504
       BROAD_ID_WIDTH,
505
       BROAD_REQ_FIFO_SIZE,
506
       BROAD_REQ_FIFO_SIZE_LOG2,
507
       MBUS_CMD_WIDTH,
508
       BREQ_FIFO_SIZE,
509
       BREQ_FIFO_SIZE_LOG2
510
      )
511
   //         \ /
512
   mesi_isc_tb_cpu2
513
    (
514
     // Inputs
515
     .clk              (clk),
516
     .rst              (rst),
517
     .cbus_addr_i      (cbus_addr),
518
     //                        \ /
519
     .cbus_cmd_i       (cbus_cmd2),
520
     //                             \ /
521
     .mbus_data_i      (mbus_data_rd),
522
     //                        \ /
523
     .mbus_ack_i       (mbus_ack[2]),
524
     //                   \ /
525
     .cpu_id_i         (2'd2),
526
     //                      \ /
527
     .tb_ins_i         (tb_ins_array[2]),
528
     //                           \ /
529
     .tb_ins_addr_i    (tb_ins_addr2),
530
     // Outputs                \ /
531
     .mbus_cmd_o       (mbus_cmd_array[2]),
532
      //                        \ /
533
     .mbus_addr_o      (mbus_addr_array[2]),
534
      //                        \ /
535
     .mbus_data_o      (mbus_data_wr_array[2]),
536
     //                        \ /
537
     .cbus_ack_o       (cbus_ack2),
538
     //                          \ /
539
     .tb_ins_ack_o     (tb_ins_ack[2])
540
 );
541
 
542
// mesi_isc_tb_cpu1
543
mesi_isc_tb_cpu  #(
544
       CBUS_CMD_WIDTH,
545
       ADDR_WIDTH,
546
       DATA_WIDTH,
547
       BROAD_TYPE_WIDTH,
548
       BROAD_ID_WIDTH,
549
       BROAD_REQ_FIFO_SIZE,
550
       BROAD_REQ_FIFO_SIZE_LOG2,
551
       MBUS_CMD_WIDTH,
552
       BREQ_FIFO_SIZE,
553
       BREQ_FIFO_SIZE_LOG2
554
      )
555
   //         \ /
556
   mesi_isc_tb_cpu1
557
    (
558
     // Inputs
559
     .clk              (clk),
560
     .rst              (rst),
561
     .cbus_addr_i      (cbus_addr),
562
     //                        \ /
563
     .cbus_cmd_i       (cbus_cmd1),
564
     //                             \ /
565
     .mbus_data_i      (mbus_data_rd),
566
     //                        \ /
567
     .mbus_ack_i       (mbus_ack[1]),
568
     //                   \ /
569
     .cpu_id_i         (2'd1),
570
     //                      \ /
571
     .tb_ins_i         (tb_ins_array[1]),
572
     //                           \ /
573
     .tb_ins_addr_i    (tb_ins_addr1),
574
     // Outputs                \ /
575
     .mbus_cmd_o       (mbus_cmd_array[1]),
576
      //                        \ /
577
     .mbus_addr_o      (mbus_addr_array[1]),
578
      //                        \ /
579
     .mbus_data_o      (mbus_data_wr_array[1]),
580
     //                        \ /
581
     .cbus_ack_o       (cbus_ack1),
582
     //                          \ /
583
     .tb_ins_ack_o     (tb_ins_ack[1])
584
 );
585
 
586
// mesi_isc_tb_cpu0
587
mesi_isc_tb_cpu  #(
588
       CBUS_CMD_WIDTH,
589
       ADDR_WIDTH,
590
       DATA_WIDTH,
591
       BROAD_TYPE_WIDTH,
592
       BROAD_ID_WIDTH,
593
       BROAD_REQ_FIFO_SIZE,
594
       BROAD_REQ_FIFO_SIZE_LOG2,
595
       MBUS_CMD_WIDTH,
596
       BREQ_FIFO_SIZE,
597
       BREQ_FIFO_SIZE_LOG2
598
      )
599
   //         \ /
600
   mesi_isc_tb_cpu0
601
    (
602
     // Inputs
603
     .clk              (clk),
604
     .rst              (rst),
605
     .cbus_addr_i      (cbus_addr),
606
     //                        \ /
607
     .cbus_cmd_i       (cbus_cmd0),
608
     //                             \ /
609
     .mbus_data_i      (mbus_data_rd),
610
     //                        \ /
611
     .mbus_ack_i       (mbus_ack[0]),
612
     //                   \ /
613
     .cpu_id_i         (2'd0),
614
     //                      \ /
615
     .tb_ins_i         (tb_ins_array[0]),
616
     //                           \ /
617
     .tb_ins_addr_i    (tb_ins_addr0),
618
     // Outputs                \ /
619
     .mbus_cmd_o       (mbus_cmd_array[0]),
620
      //                        \ /
621
     .mbus_addr_o      (mbus_addr_array[0]),
622
      //                        \ /
623
     .mbus_data_o      (mbus_data_wr_array[0]),
624
     //                        \ /
625
     .cbus_ack_o       (cbus_ack0),
626
     //                           \ /
627
     .tb_ins_ack_o     (tb_ins_ack[0])
628
 );
629
 
630
endmodule

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