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[/] [mesi_isc/] [trunk/] [src/] [tb/] [mesi_isc_tb_define.v] - Blame information for rev 2

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1 2 yaira
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MESI_ISC Project                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Yair Amitay       yair.amitay@yahoo.com               ////
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////                          www.linkedin.com/in/yairamitay      ////
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////                                                              ////
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////  Description                                                 ////
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////  mesi_isc_tb_define                                          ////
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////  -------------------                                         ////
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////  Contains the timescale and the define declaration of the    ////
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////  block tb                                                    ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//`define messages
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`define mesi_isc_debug
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// CPU instructions
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`define MESI_ISC_TB_INS_NOP 4'd0
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`define MESI_ISC_TB_INS_WR  4'd1
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`define MESI_ISC_TB_INS_RD  4'd2
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`define MESI_ISC_TB_CPU_M_STATE_IDLE        0
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`define MESI_ISC_TB_CPU_M_STATE_WR_CACHE    1
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`define MESI_ISC_TB_CPU_M_STATE_RD_CACHE    2
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`define MESI_ISC_TB_CPU_M_STATE_SEND_WR_BR  3
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`define MESI_ISC_TB_CPU_M_STATE_SEND_RD_BR  4
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`define MESI_ISC_TB_CPU_C_STATE_IDLE        0
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`define MESI_ISC_TB_CPU_C_STATE_WR_SNOOP    1
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`define MESI_ISC_TB_CPU_C_STATE_RD_SNOOP    2
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`define MESI_ISC_TB_CPU_C_STATE_EVICT_INVALIDATE 3
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`define MESI_ISC_TB_CPU_C_STATE_EVICT       4
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`define MESI_ISC_TB_CPU_C_STATE_RD_LINE_WR  5
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`define MESI_ISC_TB_CPU_C_STATE_RD_LINE_RD  6
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`define MESI_ISC_TB_CPU_C_STATE_RD_CACHE    7
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`define MESI_ISC_TB_CPU_C_STATE_WR_CACHE    8
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`define MESI_ISC_TB_CPU_MESI_M              4'b1001
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`define MESI_ISC_TB_CPU_MESI_E              4'b0101
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`define MESI_ISC_TB_CPU_MESI_S              4'b0011
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`define MESI_ISC_TB_CPU_MESI_I              4'b0000

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