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[/] [mesi_isc/] [trunk/] [syn/] [mesi_isc.map.rpt] - Blame information for rev 4

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Line No. Rev Author Line
1 4 yaira
Analysis & Synthesis report for mesi_isc
2
Tue Dec 25 13:54:13 2012
3
Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition
4
 
5
 
6
---------------------
7
; Table of Contents ;
8
---------------------
9
  1. Legal Notice
10
  2. Analysis & Synthesis Summary
11
  3. Analysis & Synthesis Settings
12
  4. Parallel Compilation
13
  5. Analysis & Synthesis Source Files Read
14
  6. Analysis & Synthesis Resource Usage Summary
15
  7. Analysis & Synthesis Resource Utilization by Entity
16
  8. General Register Statistics
17
  9. Inverted Register Statistics
18
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
19
 11. Parameter Settings for User Entity Instance: Top-level Entity: |mesi_isc
20
 12. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad
21
 13. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl
22
 14. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo
23
 15. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos
24
 16. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl
25
 17. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3
26
 18. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2
27
 19. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1
28
 20. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0
29
 21. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0"
30
 22. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1"
31
 23. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2"
32
 24. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"
33
 25. Port Connectivity Checks: "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl"
34
 26. Elapsed Time Per Partition
35
 27. Analysis & Synthesis Messages
36
 28. Analysis & Synthesis Suppressed Messages
37
 
38
 
39
 
40
----------------
41
; Legal Notice ;
42
----------------
43
Copyright (C) 1991-2012 Altera Corporation
44
Your use of Altera Corporation's design tools, logic functions
45
and other software and tools, and its AMPP partner logic
46
functions, and any output files from any of the foregoing
47
(including device programming or simulation files), and any
48
associated documentation or information are expressly subject
49
to the terms and conditions of the Altera Program License
50
Subscription Agreement, Altera MegaCore Function License
51
Agreement, or other applicable license agreement, including,
52
without limitation, that your use is for the sole purpose of
53
programming logic devices manufactured by Altera and sold by
54
Altera or its authorized distributors.  Please refer to the
55
applicable agreement for further details.
56
 
57
 
58
 
59
+------------------------------------------------------------------------------------+
60
; Analysis & Synthesis Summary                                                       ;
61
+------------------------------------+-----------------------------------------------+
62
; Analysis & Synthesis Status        ; Successful - Tue Dec 25 13:54:13 2012         ;
63
; Quartus II 32-bit Version          ; 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition ;
64
; Revision Name                      ; mesi_isc                                      ;
65
; Top-level Entity Name              ; mesi_isc                                      ;
66
; Family                             ; Cyclone IV GX                                 ;
67
; Total logic elements               ; 863                                           ;
68
;     Total combinational functions  ; 481                                           ;
69
;     Dedicated logic registers      ; 636                                           ;
70
; Total registers                    ; 636                                           ;
71
; Total pins                         ; 194                                           ;
72
; Total virtual pins                 ; 0                                             ;
73
; Total memory bits                  ; 0                                             ;
74
; Embedded Multiplier 9-bit elements ; 0                                             ;
75
; Total GXB Receiver Channel PCS     ; 0                                             ;
76
; Total GXB Receiver Channel PMA     ; 0                                             ;
77
; Total GXB Transmitter Channel PCS  ; 0                                             ;
78
; Total GXB Transmitter Channel PMA  ; 0                                             ;
79
; Total PLLs                         ; 0                                             ;
80
+------------------------------------+-----------------------------------------------+
81
 
82
 
83
+----------------------------------------------------------------------------------------------------------------------+
84
; Analysis & Synthesis Settings                                                                                        ;
85
+----------------------------------------------------------------------------+--------------------+--------------------+
86
; Option                                                                     ; Setting            ; Default Value      ;
87
+----------------------------------------------------------------------------+--------------------+--------------------+
88
; Top-level entity name                                                      ; mesi_isc           ; mesi_isc           ;
89
; Family name                                                                ; Cyclone IV GX      ; Cyclone IV GX      ;
90
; Use smart compilation                                                      ; Off                ; Off                ;
91
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
92
; Enable compact report table                                                ; Off                ; Off                ;
93
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
94
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
95
; Preserve fewer node names                                                  ; On                 ; On                 ;
96
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
97
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
98
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
99
; State Machine Processing                                                   ; Auto               ; Auto               ;
100
; Safe State Machine                                                         ; Off                ; Off                ;
101
; Extract Verilog State Machines                                             ; On                 ; On                 ;
102
; Extract VHDL State Machines                                                ; On                 ; On                 ;
103
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
104
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
105
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
106
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
107
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
108
; Parallel Synthesis                                                         ; On                 ; On                 ;
109
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
110
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
111
; Power-Up Don't Care                                                        ; On                 ; On                 ;
112
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
113
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
114
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
115
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
116
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
117
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
118
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
119
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
120
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
121
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
122
; Carry Chain Length                                                         ; 70                 ; 70                 ;
123
; Auto Carry Chains                                                          ; On                 ; On                 ;
124
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
125
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
126
; Auto ROM Replacement                                                       ; On                 ; On                 ;
127
; Auto RAM Replacement                                                       ; On                 ; On                 ;
128
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
129
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
130
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
131
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
132
; Strict RAM Replacement                                                     ; Off                ; Off                ;
133
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
134
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
135
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
136
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
137
; Auto Resource Sharing                                                      ; Off                ; Off                ;
138
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
139
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
140
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
141
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
142
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
143
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
144
; Report Parameter Settings                                                  ; On                 ; On                 ;
145
; Report Source Assignments                                                  ; On                 ; On                 ;
146
; Report Connectivity Checks                                                 ; On                 ; On                 ;
147
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
148
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
149
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
150
; HDL message level                                                          ; Level2             ; Level2             ;
151
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
152
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
153
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
154
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
155
; Clock MUX Protection                                                       ; On                 ; On                 ;
156
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
157
; Block Design Naming                                                        ; Auto               ; Auto               ;
158
; SDC constraint protection                                                  ; Off                ; Off                ;
159
; Synthesis Effort                                                           ; Auto               ; Auto               ;
160
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
161
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
162
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
163
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
164
; Synthesis Seed                                                             ; 1                  ; 1                  ;
165
+----------------------------------------------------------------------------+--------------------+--------------------+
166
 
167
 
168
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
169
+-------------------------------------+
170
; Parallel Compilation                ;
171
+----------------------------+--------+
172
; Processors                 ; Number ;
173
+----------------------------+--------+
174
; Number detected on machine ; 4      ;
175
; Maximum allowed            ; 1      ;
176
+----------------------------+--------+
177
 
178
 
179
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
180
; Analysis & Synthesis Source Files Read                                                                                                                            ;
181
+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+
182
; File Name with User-Entered Path      ; Used in Netlist ; File Type              ; File Name with Absolute Path                                         ; Library ;
183
+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+
184
; ../src/rtl/mesi_isc_define.v          ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v          ;         ;
185
; ../src/rtl/mesi_isc_broad_cntl.v      ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v      ;         ;
186
; ../src/rtl/mesi_isc_broad.v           ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v           ;         ;
187
; ../src/rtl/mesi_isc_breq_fifos_cntl.v ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v ;         ;
188
; ../src/rtl/mesi_isc_breq_fifos.v      ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v      ;         ;
189
; ../src/rtl/mesi_isc_basic_fifo.v      ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v      ;         ;
190
; ../src/rtl/mesi_isc.v                 ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v                 ;         ;
191
+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+
192
 
193
 
194
+---------------------------------------------+
195
; Analysis & Synthesis Resource Usage Summary ;
196
+----------------------+----------------------+
197
; Resource             ; Usage                ;
198
+----------------------+----------------------+
199
; I/O pins             ; 194                  ;
200
; Maximum fan-out node ; clk~input            ;
201
; Maximum fan-out      ; 636                  ;
202
; Total fan-out        ; 4466                 ;
203
; Average fan-out      ; 2.97                 ;
204
+----------------------+----------------------+
205
 
206
 
207
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
208
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                    ;
209
+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+
210
; Compilation Hierarchy Node                                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                 ; Library Name ;
211
+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+
212
; |mesi_isc                                                 ; 481 (0)           ; 636 (0)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 194  ; 0            ; |mesi_isc                                                                                           ;              ;
213
;    |mesi_isc_breq_fifos:mesi_isc_breq_fifos|              ; 312 (0)           ; 440 (0)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos                                                   ;              ;
214
;       |mesi_isc_basic_fifo:fifo_0|                        ; 41 (41)           ; 106 (106)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0                        ;              ;
215
;       |mesi_isc_basic_fifo:fifo_1|                        ; 41 (41)           ; 106 (106)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1                        ;              ;
216
;       |mesi_isc_basic_fifo:fifo_2|                        ; 41 (41)           ; 106 (106)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2                        ;              ;
217
;       |mesi_isc_basic_fifo:fifo_3|                        ; 41 (41)           ; 106 (106)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3                        ;              ;
218
;       |mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl| ; 148 (148)         ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ;              ;
219
;    |mesi_isc_broad:mesi_isc_broad|                        ; 169 (0)           ; 196 (0)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_broad:mesi_isc_broad                                                             ;              ;
220
;       |mesi_isc_basic_fifo:broad_fifo|                    ; 124 (124)         ; 186 (186)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo                              ;              ;
221
;       |mesi_isc_broad_cntl:mesi_isc_broad_cntl|           ; 45 (45)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl                     ;              ;
222
+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+
223
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
224
 
225
 
226
+------------------------------------------------------+
227
; General Register Statistics                          ;
228
+----------------------------------------------+-------+
229
; Statistic                                    ; Value ;
230
+----------------------------------------------+-------+
231
; Total registers                              ; 636   ;
232
; Number of registers using Synchronous Clear  ; 0     ;
233
; Number of registers using Synchronous Load   ; 136   ;
234
; Number of registers using Asynchronous Clear ; 636   ;
235
; Number of registers using Asynchronous Load  ; 0     ;
236
; Number of registers using Clock Enable       ; 427   ;
237
; Number of registers using Preset             ; 0     ;
238
+----------------------------------------------+-------+
239
 
240
 
241
+-----------------------------------------------------------------------------------------------------------------------+
242
; Inverted Register Statistics                                                                                          ;
243
+-------------------------------------------------------------------------------------------------------------+---------+
244
; Inverted Register                                                                                           ; Fan out ;
245
+-------------------------------------------------------------------------------------------------------------+---------+
246
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[0] ; 9       ;
247
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|status_empty                             ; 39      ;
248
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty                             ; 39      ;
249
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty                             ; 39      ;
250
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|status_empty                             ; 39      ;
251
; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_empty                                   ; 47      ;
252
; Total number of inverted registers = 6                                                                      ;         ;
253
+-------------------------------------------------------------------------------------------------------------+---------+
254
 
255
 
256
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
257
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                      ;
258
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+
259
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                                                                                                            ; Example Multiplexer Output ;
260
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+
261
; 5:1                ; 34 bits   ; 102 LEs       ; 68 LEs               ; 34 LEs                 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[27]                               ;                            ;
262
; 5:1                ; 34 bits   ; 102 LEs       ; 68 LEs               ; 34 LEs                 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[33]                               ;                            ;
263
; 5:1                ; 34 bits   ; 102 LEs       ; 68 LEs               ; 34 LEs                 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[29]                               ;                            ;
264
; 5:1                ; 34 bits   ; 102 LEs       ; 68 LEs               ; 34 LEs                 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[25]                               ;                            ;
265
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3]        ;                            ;
266
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2]            ;                            ;
267
; 9:1                ; 36 bits   ; 216 LEs       ; 108 LEs              ; 108 LEs                ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[21]                                     ;                            ;
268
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0] ;                            ;
269
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+
270
 
271
 
272
+--------------------------------------------------------------------------+
273
; Parameter Settings for User Entity Instance: Top-level Entity: |mesi_isc ;
274
+--------------------------+-------+---------------------------------------+
275
; Parameter Name           ; Value ; Type                                  ;
276
+--------------------------+-------+---------------------------------------+
277
; CBUS_CMD_WIDTH           ; 3     ; Signed Integer                        ;
278
; ADDR_WIDTH               ; 32    ; Signed Integer                        ;
279
; BROAD_TYPE_WIDTH         ; 2     ; Signed Integer                        ;
280
; BROAD_ID_WIDTH           ; 5     ; Signed Integer                        ;
281
; BROAD_REQ_FIFO_SIZE      ; 4     ; Signed Integer                        ;
282
; BROAD_REQ_FIFO_SIZE_LOG2 ; 2     ; Signed Integer                        ;
283
; MBUS_CMD_WIDTH           ; 3     ; Signed Integer                        ;
284
; BREQ_FIFO_SIZE           ; 2     ; Signed Integer                        ;
285
; BREQ_FIFO_SIZE_LOG2      ; 1     ; Signed Integer                        ;
286
+--------------------------+-------+---------------------------------------+
287
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
288
 
289
 
290
+----------------------------------------------------------------------------+
291
; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad ;
292
+--------------------------+-------+-----------------------------------------+
293
; Parameter Name           ; Value ; Type                                    ;
294
+--------------------------+-------+-----------------------------------------+
295
; CBUS_CMD_WIDTH           ; 3     ; Signed Integer                          ;
296
; ADDR_WIDTH               ; 32    ; Signed Integer                          ;
297
; BROAD_TYPE_WIDTH         ; 2     ; Signed Integer                          ;
298
; BROAD_ID_WIDTH           ; 5     ; Signed Integer                          ;
299
; BROAD_REQ_FIFO_SIZE      ; 4     ; Signed Integer                          ;
300
; BROAD_REQ_FIFO_SIZE_LOG2 ; 2     ; Signed Integer                          ;
301
+--------------------------+-------+-----------------------------------------+
302
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
303
 
304
 
305
+--------------------------------------------------------------------------------------------------------------------+
306
; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl ;
307
+------------------+-------+-----------------------------------------------------------------------------------------+
308
; Parameter Name   ; Value ; Type                                                                                    ;
309
+------------------+-------+-----------------------------------------------------------------------------------------+
310
; CBUS_CMD_WIDTH   ; 3     ; Signed Integer                                                                          ;
311
; BROAD_TYPE_WIDTH ; 2     ; Signed Integer                                                                          ;
312
; BROAD_ID_WIDTH   ; 5     ; Signed Integer                                                                          ;
313
+------------------+-------+-----------------------------------------------------------------------------------------+
314
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
315
 
316
 
317
+-----------------------------------------------------------------------------------------------------------+
318
; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo ;
319
+----------------+-------+----------------------------------------------------------------------------------+
320
; Parameter Name ; Value ; Type                                                                             ;
321
+----------------+-------+----------------------------------------------------------------------------------+
322
; DATA_WIDTH     ; 41    ; Signed Integer                                                                   ;
323
; FIFO_SIZE      ; 4     ; Signed Integer                                                                   ;
324
; FIFO_SIZE_LOG2 ; 2     ; Signed Integer                                                                   ;
325
+----------------+-------+----------------------------------------------------------------------------------+
326
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
327
 
328
 
329
+--------------------------------------------------------------------------------------+
330
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos ;
331
+---------------------+-------+--------------------------------------------------------+
332
; Parameter Name      ; Value ; Type                                                   ;
333
+---------------------+-------+--------------------------------------------------------+
334
; MBUS_CMD_WIDTH      ; 3     ; Signed Integer                                         ;
335
; ADDR_WIDTH          ; 32    ; Signed Integer                                         ;
336
; BROAD_TYPE_WIDTH    ; 2     ; Signed Integer                                         ;
337
; BROAD_ID_WIDTH      ; 5     ; Signed Integer                                         ;
338
; BREQ_FIFO_SIZE      ; 2     ; Signed Integer                                         ;
339
; BREQ_FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                         ;
340
+---------------------+-------+--------------------------------------------------------+
341
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
342
 
343
 
344
+----------------------------------------------------------------------------------------------------------------------------------------+
345
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ;
346
+------------------+-------+-------------------------------------------------------------------------------------------------------------+
347
; Parameter Name   ; Value ; Type                                                                                                        ;
348
+------------------+-------+-------------------------------------------------------------------------------------------------------------+
349
; MBUS_CMD_WIDTH   ; 3     ; Signed Integer                                                                                              ;
350
; ADDR_WIDTH       ; 32    ; Signed Integer                                                                                              ;
351
; BROAD_TYPE_WIDTH ; 2     ; Signed Integer                                                                                              ;
352
; BROAD_ID_WIDTH   ; 5     ; Signed Integer                                                                                              ;
353
+------------------+-------+-------------------------------------------------------------------------------------------------------------+
354
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
355
 
356
 
357
+-----------------------------------------------------------------------------------------------------------------+
358
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3 ;
359
+----------------+-------+----------------------------------------------------------------------------------------+
360
; Parameter Name ; Value ; Type                                                                                   ;
361
+----------------+-------+----------------------------------------------------------------------------------------+
362
; DATA_WIDTH     ; 41    ; Signed Integer                                                                         ;
363
; FIFO_SIZE      ; 2     ; Signed Integer                                                                         ;
364
; FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                                                         ;
365
+----------------+-------+----------------------------------------------------------------------------------------+
366
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
367
 
368
 
369
+-----------------------------------------------------------------------------------------------------------------+
370
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2 ;
371
+----------------+-------+----------------------------------------------------------------------------------------+
372
; Parameter Name ; Value ; Type                                                                                   ;
373
+----------------+-------+----------------------------------------------------------------------------------------+
374
; DATA_WIDTH     ; 41    ; Signed Integer                                                                         ;
375
; FIFO_SIZE      ; 2     ; Signed Integer                                                                         ;
376
; FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                                                         ;
377
+----------------+-------+----------------------------------------------------------------------------------------+
378
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
379
 
380
 
381
+-----------------------------------------------------------------------------------------------------------------+
382
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1 ;
383
+----------------+-------+----------------------------------------------------------------------------------------+
384
; Parameter Name ; Value ; Type                                                                                   ;
385
+----------------+-------+----------------------------------------------------------------------------------------+
386
; DATA_WIDTH     ; 41    ; Signed Integer                                                                         ;
387
; FIFO_SIZE      ; 2     ; Signed Integer                                                                         ;
388
; FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                                                         ;
389
+----------------+-------+----------------------------------------------------------------------------------------+
390
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
391
 
392
 
393
+-----------------------------------------------------------------------------------------------------------------+
394
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0 ;
395
+----------------+-------+----------------------------------------------------------------------------------------+
396
; Parameter Name ; Value ; Type                                                                                   ;
397
+----------------+-------+----------------------------------------------------------------------------------------+
398
; DATA_WIDTH     ; 41    ; Signed Integer                                                                         ;
399
; FIFO_SIZE      ; 2     ; Signed Integer                                                                         ;
400
; FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                                                         ;
401
+----------------+-------+----------------------------------------------------------------------------------------+
402
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
403
 
404
 
405
+------------------------------------------------------------------------------------------------------------------------+
406
; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0"                         ;
407
+--------------+--------+----------+-------------------------------------------------------------------------------------+
408
; Port         ; Type   ; Severity ; Details                                                                             ;
409
+--------------+--------+----------+-------------------------------------------------------------------------------------+
410
; data_o[6..5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
411
+--------------+--------+----------+-------------------------------------------------------------------------------------+
412
 
413
 
414
+------------------------------------------------------------------------------------------------------------------------+
415
; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1"                         ;
416
+--------------+--------+----------+-------------------------------------------------------------------------------------+
417
; Port         ; Type   ; Severity ; Details                                                                             ;
418
+--------------+--------+----------+-------------------------------------------------------------------------------------+
419
; data_o[6..5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
420
+--------------+--------+----------+-------------------------------------------------------------------------------------+
421
 
422
 
423
+------------------------------------------------------------------------------------------------------------------------+
424
; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2"                         ;
425
+--------------+--------+----------+-------------------------------------------------------------------------------------+
426
; Port         ; Type   ; Severity ; Details                                                                             ;
427
+--------------+--------+----------+-------------------------------------------------------------------------------------+
428
; data_o[6..5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
429
+--------------+--------+----------+-------------------------------------------------------------------------------------+
430
 
431
 
432
+------------------------------------------------------------------------------------------------------------------------+
433
; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"                         ;
434
+--------------+--------+----------+-------------------------------------------------------------------------------------+
435
; Port         ; Type   ; Severity ; Details                                                                             ;
436
+--------------+--------+----------+-------------------------------------------------------------------------------------+
437
; data_o[6..5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
438
+--------------+--------+----------+-------------------------------------------------------------------------------------+
439
 
440
 
441
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
442
; Port Connectivity Checks: "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl"                                                                                            ;
443
+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
444
; Port                       ; Type  ; Severity ; Details                                                                                                                                      ;
445
+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
446
; fifo_status_almost_empty_i ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
447
; fifo_status_almost_full_i  ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
448
+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
449
 
450
 
451
+-------------------------------+
452
; Elapsed Time Per Partition    ;
453
+----------------+--------------+
454
; Partition Name ; Elapsed Time ;
455
+----------------+--------------+
456
; Top            ; 00:00:02     ;
457
+----------------+--------------+
458
 
459
 
460
+-------------------------------+
461
; Analysis & Synthesis Messages ;
462
+-------------------------------+
463
Info: *******************************************************************
464
Info: Running Quartus II 32-bit Analysis & Synthesis
465
    Info: Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition
466
    Info: Processing started: Tue Dec 25 13:54:09 2012
467
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc
468
Warning (20028): Parallel compilation is not licensed and has been disabled
469
Info (12021): Found 0 design units, including 0 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v
470
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v
471
    Info (12023): Found entity 1: mesi_isc_broad_cntl
472
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v
473
    Info (12023): Found entity 1: mesi_isc_broad
474
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v
475
    Info (12023): Found entity 1: mesi_isc_breq_fifos_cntl
476
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v
477
    Info (12023): Found entity 1: mesi_isc_breq_fifos
478
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v
479
    Info (12023): Found entity 1: mesi_isc_basic_fifo
480
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v
481
    Info (12023): Found entity 1: mesi_isc
482
Info (12127): Elaborating entity "mesi_isc" for the top level hierarchy
483
Info (12128): Elaborating entity "mesi_isc_broad" for hierarchy "mesi_isc_broad:mesi_isc_broad"
484
Info (12128): Elaborating entity "mesi_isc_broad_cntl" for hierarchy "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl"
485
Info (12128): Elaborating entity "mesi_isc_basic_fifo" for hierarchy "mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"
486
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (2)
487
Warning (10240): Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
488
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (2)
489
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (2)
490
Info (12128): Elaborating entity "mesi_isc_breq_fifos" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos"
491
Info (12128): Elaborating entity "mesi_isc_breq_fifos_cntl" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl"
492
Warning (10230): Verilog HDL assignment warning at mesi_isc_breq_fifos_cntl.v(371): truncated value with size 32 to match size of target (3)
493
Info (12128): Elaborating entity "mesi_isc_basic_fifo" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"
494
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (1)
495
Warning (10240): Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
496
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (1)
497
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (1)
498
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
499
Info (13000): Registers with preset signals will power-up high
500
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
501
Info (286030): Timing-Driven Synthesis is running
502
Info (144001): Generated suppressed messages file /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg
503
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
504
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
505
Info (21057): Implemented 1101 device resources after synthesis - the final resource count might be different
506
    Info (21058): Implemented 146 input pins
507
    Info (21059): Implemented 48 output pins
508
    Info (21061): Implemented 907 logic cells
509
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings
510
    Info: Peak virtual memory: 370 megabytes
511
    Info: Processing ended: Tue Dec 25 13:54:13 2012
512
    Info: Elapsed time: 00:00:04
513
    Info: Total CPU time (on all processors): 00:00:04
514
 
515
 
516
+------------------------------------------+
517
; Analysis & Synthesis Suppressed Messages ;
518
+------------------------------------------+
519
The suppressed messages can be found in /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg.
520
 
521
 

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