Subversion Repositories mesi_isc

## Generated SDC file "mesi_isc.out.sdc"

## Copyright (C) 1991-2012 Altera Corporation

## Your use of Altera Corporation's design tools, logic functions

## and other software and tools, and its AMPP partner logic

## functions, and any output files from any of the foregoing

## (including device programming or simulation files), and any

## associated documentation or information are expressly subject

## to the terms and conditions of the Altera Program License

## Subscription Agreement, Altera MegaCore Function License

## Agreement, or other applicable license agreement, including,

## without limitation, that your use is for the sole purpose of

## programming logic devices manufactured by Altera and sold by

## Altera or its authorized distributors.  Please refer to the

## applicable agreement for further details.

## VENDOR  "Altera"

## PROGRAM "Quartus II"

## VERSION "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition"

## DATE    "Tue Nov  6 14:51:56 2012"

##

## DEVICE  "EP4CGX30CF23C6"

##

#**************************************************************

# Time Information

#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************

# Create Clock

#**************************************************************

create_clock -name {clk} -period 1.000 -waveform { 0.000 0.500 } [get_ports {clk}]

#**************************************************************

# Create Generated Clock

#**************************************************************

#**************************************************************

# Set Clock Latency

#**************************************************************

#**************************************************************

# Set Clock Uncertainty

#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}]  0.020

set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}]  0.020

set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}]  0.020

set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}]  0.020

#**************************************************************

# Set Input Delay

#**************************************************************

set_input_delay -add_delay  -clock [get_clocks {clk}]  0.100 [get_ports {cbus_ack*}]

set_input_delay -add_delay  -clock [get_clocks {clk}]  0.100 [get_ports {mbus_addr*}]

set_input_delay -add_delay  -clock [get_clocks {clk}]  0.100 [get_ports {mbus_cmd*}]

#**************************************************************

# Set Output Delay

#**************************************************************

set_output_delay -add_delay  -clock [get_clocks {clk}]  0.100 [get_ports {cbus_addr_o*}]

set_output_delay -add_delay  -clock [get_clocks {clk}]  0.100 [get_ports {cbus_cmd*}]

set_output_delay -add_delay  -clock [get_clocks {clk}]  0.100 [get_ports {mbus_ack*}]

#**************************************************************

# Set Clock Groups

#**************************************************************

#**************************************************************

# Set False Path

#**************************************************************

#**************************************************************

# Set Multicycle Path

#**************************************************************

#**************************************************************

# Set Maximum Delay

#**************************************************************

#**************************************************************

# Set Minimum Delay

#**************************************************************

#**************************************************************

# Set Input Transition

#**************************************************************