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[/] [mesi_isc/] [trunk/] [syn/] [rpt/] [mesi_isc-Flow Summary.rpt] - Blame information for rev 4

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1 4 yaira
Flow Summary report for mesi_isc
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Tue Nov  6 20:48:09 2012
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Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition
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; Table of Contents ;
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  1. Legal Notice
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  2. Flow Summary
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2012 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors.  Please refer to the
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applicable agreement for further details.
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+------------------------------------------------------------------------------------+
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; Flow Summary                                                                       ;
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+------------------------------------+-----------------------------------------------+
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; Flow Status                        ; Successful - Tue Nov  6 14:54:24 2012         ;
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; Quartus II 32-bit Version          ; 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition ;
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; Revision Name                      ; mesi_isc                                      ;
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; Top-level Entity Name              ; mesi_isc                                      ;
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; Family                             ; Cyclone IV GX                                 ;
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; Total logic elements               ; 72 / 29,440 ( < 1 % )                         ;
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;     Total combinational functions  ; 72 / 29,440 ( < 1 % )                         ;
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;     Dedicated logic registers      ; 45 / 29,440 ( < 1 % )                         ;
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; Total registers                    ; 45                                            ;
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; Total pins                         ; 190 / 307 ( 62 % )                            ;
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; Total virtual pins                 ; 0                                             ;
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; Total memory bits                  ; 0 / 1,105,920 ( 0 % )                         ;
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; Embedded Multiplier 9-bit elements ; 0 / 160 ( 0 % )                               ;
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; Total GXB Receiver Channel PCS     ; 0 / 4 ( 0 % )                                 ;
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; Total GXB Receiver Channel PMA     ; 0 / 4 ( 0 % )                                 ;
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; Total GXB Transmitter Channel PCS  ; 0 / 4 ( 0 % )                                 ;
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; Total GXB Transmitter Channel PMA  ; 0 / 4 ( 0 % )                                 ;
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; Total PLLs                         ; 0 / 6 ( 0 % )                                 ;
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; Device                             ; EP4CGX30CF23C6                                ;
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; Timing Models                      ; Final                                         ;
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+------------------------------------+-----------------------------------------------+
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