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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1K test app definitions                                   ////
////                                                              ////
////  This file is part of the OR1K test application              ////
////  http://www.opencores.org/cores/or1k/xess/                   ////
////                                                              ////
////  Description                                                 ////
////  DEfine target technology etc. Right now FIFOs are available ////
////  only for Xilinx Virtex FPGAs. (TARGET_VIRTEX)               ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, damjan.lampret@opencores.org          ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xsv_fpga_defines.v,v $
// Revision 1.4  2004/04/05 08:44:35  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2  2002/03/29 20:58:51  lampret
// Changed hardcoded address for fake MC to use a define.
//
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
// First import of the "new" XESS XSV environment.
//
//
//
 
 
//
// Define FPGA manufacturer
//
//`define GENERIC_FPGA
//`define ALTERA_FPGA
`define XILINX_FPGA
 
// 
// Define FPGA Model (comment all out for ALTERA)
//
//`define SPARTAN2
//`define SPARTAN3
//`define SPARTAN3E
`define SPARTAN3A
//`define VIRTEX
//`define VIRTEX2
//`define VIRTEX4
//`define VIRTEX5
 
 
//
// Memory
//
`define MEMORY_ADR_WIDTH   13   //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
                                                                //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth 
                                                                //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth
 
//
// Memory type  (uncomment something if ASIC or if you want generic memory)
//
//`define GENERIC_MEMORY
//`define AVANT_ATP
//`define VIRAGE_SSP
//`define VIRTUALSILICON_SSP
 
 
//
// TAP selection
//
//`define GENERIC_TAP
`define FPGA_TAP
 
//
// Clock Division selection
//
//`define NO_CLOCK_DIVISION
//`define GENERIC_CLOCK_DIVISION
`define FPGA_CLOCK_DIVISION             //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation
                                                                //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken
 
//
// Define division
//
`define CLOCK_DIVISOR 5         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
                                                        //in FPGA case, check minsoc_clock_manager for allowed divisors
                                                        //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
 
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
//
//`define START_UP
 
//
// Connected modules
//
`define UART
//`define ETHERNET
 
//
// Ethernet reset
//
//`define ETH_RESET     1'b0
`define ETH_RESET       1'b1
 
//
// Interrupts
//
`define APP_INT_RES1    1:0
`define APP_INT_UART    2
`define APP_INT_RES2    3
`define APP_INT_ETH     4
`define APP_INT_PS2     5
`define APP_INT_RES3    19:6
 
//
// Address map
//
`define APP_ADDR_DEC_W  8
`define APP_ADDR_SRAM   `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH  `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W  4
`define APP_ADDR_PERIP  `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI    `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH    `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO  `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART   `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2    `APP_ADDR_DEC_W'h94
`define APP_ADDR_RES1   `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2   `APP_ADDR_DEC_W'h9f
 
//
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
//
`ifdef GENERIC_FPGA
        `define GENERIC_TAP
        `define GENERIC_MEMORY
        `ifndef NO_CLOCK_DIVISION
                `define GENERIC_CLOCK_DIVISION
        `endif
`endif

Line No.	Rev	Author	Line
1	2	rfajardo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1K test app definitions ////`
4			`//// ////`
5			`//// This file is part of the OR1K test application ////`
6			`//// http://www.opencores.org/cores/or1k/xess/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// DEfine target technology etc. Right now FIFOs are available ////`
10			`//// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - nothing really ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, damjan.lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: xsv_fpga_defines.v,v $`
48			`// Revision 1.4 2004/04/05 08:44:35 lampret`
49			`// Merged branch_qmem into main tree.`
50			`//`
51			`// Revision 1.2 2002/03/29 20:58:51 lampret`
52			`// Changed hardcoded address for fake MC to use a define.`
53			`//`
54			`// Revision 1.1.1.1 2002/03/21 16:55:44 lampret`
55			`// First import of the "new" XESS XSV environment.`
56			`//`
57			`//`
58			`//`
59
60
61			`//`
62			`// Define FPGA manufacturer`
63			`//`
64			//`define GENERIC_FPGA
65			//`define ALTERA_FPGA
66			`define XILINX_FPGA
67
68			`//`
69			`// Define FPGA Model (comment all out for ALTERA)`
70			`//`
71			//`define SPARTAN2
72			//`define SPARTAN3
73			//`define SPARTAN3E
74			`define SPARTAN3A
75			//`define VIRTEX
76			//`define VIRTEX2
77			//`define VIRTEX4
78			//`define VIRTEX5
79
80
81			`//`
82			`// Memory`
83			`//`
84			`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
85			`//Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth`
86			`//the memory data width is 32 bit, memory amount in Bytes = 4*memory depth`
87
88			`//`
89			`// Memory type (uncomment something if ASIC or if you want generic memory)`
90			`//`
91			//`define GENERIC_MEMORY
92			//`define AVANT_ATP
93			//`define VIRAGE_SSP
94			//`define VIRTUALSILICON_SSP
95
96
97			`//`
98			`// TAP selection`
99			`//`
100			//`define GENERIC_TAP
101			`define FPGA_TAP
102
103			`//`
104			`// Clock Division selection`
105			`//`
106			//`define NO_CLOCK_DIVISION
107			//`define GENERIC_CLOCK_DIVISION
108			`define FPGA_CLOCK_DIVISION //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation
109			`//if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken`
110
111			`//`
112			`// Define division`
113			`//`
114			`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
115			`//in FPGA case, check minsoc_clock_manager for allowed divisors`
116			`//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD`
117
118			`//`
119			`// Start-up circuit (only necessary later to load firmware automatically from SPI memory)`
120			`//`
121			//`define START_UP
122
123			`//`
124			`// Connected modules`
125			`//`
126			`define UART
127			//`define ETHERNET
128
129			`//`
130			`// Ethernet reset`
131			`//`
132			//`define ETH_RESET 1'b0
133			`define ETH_RESET 1'b1
134
135			`//`
136			`// Interrupts`
137			`//`
138			`define APP_INT_RES1 1:0
139			`define APP_INT_UART 2
140			`define APP_INT_RES2 3
141			`define APP_INT_ETH 4
142			`define APP_INT_PS2 5
143			`define APP_INT_RES3 19:6
144
145			`//`
146			`// Address map`
147			`//`
148			`define APP_ADDR_DEC_W 8
149			`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
150			`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
151			`define APP_ADDR_DECP_W 4
152			`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
153			`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
154			`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
155			`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
156			`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
157			`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
158			`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
159			`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
160
161			`//`
162			`// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen`
163			`// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set`
164			`//`
165			`ifdef GENERIC_FPGA
166			`define GENERIC_TAP
167			`define GENERIC_MEMORY
168			`ifndef NO_CLOCK_DIVISION
169			`define GENERIC_CLOCK_DIVISION
170			`endif
171			`endif

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[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [std/] [minsoc_defines.v] - Blame information for rev 2