OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [std/] [minsoc_defines.v] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rfajardo
//
2
// Define FPGA manufacturer
3
//
4
//`define GENERIC_FPGA
5
//`define ALTERA_FPGA
6
`define XILINX_FPGA
7
 
8
// 
9
// Define FPGA Model (comment all out for ALTERA)
10
//
11
//`define SPARTAN2
12
//`define SPARTAN3
13
//`define SPARTAN3E
14
`define SPARTAN3A
15
//`define VIRTEX
16
//`define VIRTEX2
17
//`define VIRTEX4
18
//`define VIRTEX5
19
 
20
 
21
//
22
// Memory
23
//
24
`define MEMORY_ADR_WIDTH   13   //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
25
                                                                //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth 
26
                                                                //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth
27
 
28
//
29 7 rfajardo
// Memory type  (uncomment something if ASIC or generic memory)
30 2 rfajardo
//
31
//`define GENERIC_MEMORY
32
//`define AVANT_ATP
33
//`define VIRAGE_SSP
34
//`define VIRTUALSILICON_SSP
35
 
36
 
37
//
38
// TAP selection
39
//
40
//`define GENERIC_TAP
41
`define FPGA_TAP
42
 
43
//
44
// Clock Division selection
45
//
46
//`define NO_CLOCK_DIVISION
47
//`define GENERIC_CLOCK_DIVISION
48
`define FPGA_CLOCK_DIVISION             //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation
49
                                                                //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken
50
 
51
//
52
// Define division
53
//
54
`define CLOCK_DIVISOR 5         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
55
                                                        //in FPGA case, check minsoc_clock_manager for allowed divisors
56
                                                        //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
57
 
58
//
59 7 rfajardo
// Reset polarity
60
//
61
//`define NEGATIVE_RESET;      //rstn
62
`define POSITIVE_RESET;      //rst
63
 
64
//
65 2 rfajardo
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
66
//
67
//`define START_UP
68
 
69
//
70
// Connected modules
71
//
72
`define UART
73
//`define ETHERNET
74
 
75
//
76
// Ethernet reset
77
//
78
//`define ETH_RESET     1'b0
79
`define ETH_RESET       1'b1
80
 
81
//
82
// Interrupts
83
//
84
`define APP_INT_RES1    1:0
85
`define APP_INT_UART    2
86
`define APP_INT_RES2    3
87
`define APP_INT_ETH     4
88
`define APP_INT_PS2     5
89
`define APP_INT_RES3    19:6
90
 
91
//
92
// Address map
93
//
94
`define APP_ADDR_DEC_W  8
95
`define APP_ADDR_SRAM   `APP_ADDR_DEC_W'h00
96
`define APP_ADDR_FLASH  `APP_ADDR_DEC_W'h04
97
`define APP_ADDR_DECP_W  4
98
`define APP_ADDR_PERIP  `APP_ADDR_DECP_W'h9
99
`define APP_ADDR_SPI    `APP_ADDR_DEC_W'h97
100
`define APP_ADDR_ETH    `APP_ADDR_DEC_W'h92
101
`define APP_ADDR_AUDIO  `APP_ADDR_DEC_W'h9d
102
`define APP_ADDR_UART   `APP_ADDR_DEC_W'h90
103
`define APP_ADDR_PS2    `APP_ADDR_DEC_W'h94
104
`define APP_ADDR_RES1   `APP_ADDR_DEC_W'h9e
105
`define APP_ADDR_RES2   `APP_ADDR_DEC_W'h9f
106
 
107
//
108
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
109
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
110
//
111
`ifdef GENERIC_FPGA
112
        `define GENERIC_TAP
113
        `define GENERIC_MEMORY
114
        `ifndef NO_CLOCK_DIVISION
115
                `define GENERIC_CLOCK_DIVISION
116
        `endif
117
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.