OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [tags/] [release-0.9/] [sim/] [bin/] [minsoc_model.txt] - Blame information for rev 42

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Line No. Rev Author Line
1 2 rfajardo
+incdir+../../bench/verilog
2
+incdir+../../bench/verilog/vpi
3 10 rfajardo
+incdir+../../bench/verilog/sim_lib
4 2 rfajardo
+incdir+../../rtl/verilog
5
+incdir+../../rtl/verilog/minsoc_startup
6
+incdir+../../rtl/verilog/or1200/rtl/verilog
7
+incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
8
+incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
9
+incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
10
+incdir+../../rtl/verilog/uart16550/rtl/verilog
11 31 rfajardo
+incdir+../../rtl/verilog/ethmac/rtl/verilog
12
../../bench/verilog/minsoc_bench_defines.v
13 2 rfajardo
../../bench/verilog/minsoc_bench.v
14
../../bench/verilog/minsoc_memory_model.v
15 31 rfajardo
../../bench/verilog/vpi/dbg_comm_vpi.v
16 10 rfajardo
../../bench/verilog/sim_lib/fpga_memory_primitives.v
17 31 rfajardo
../../rtl/verilog/minsoc_top.v
18
../../rtl/verilog/minsoc_startup/spi_top.v
19
../../rtl/verilog/minsoc_startup/spi_defines.v
20
../../rtl/verilog/minsoc_startup/spi_shift.v
21
../../rtl/verilog/minsoc_startup/spi_clgen.v
22
../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
23 2 rfajardo
../../rtl/verilog/minsoc_tc_top.v
24 31 rfajardo
../../rtl/verilog/minsoc_onchip_ram.v
25 2 rfajardo
../../rtl/verilog/minsoc_clock_manager.v
26 31 rfajardo
#../../rtl/verilog/minsoc_onchip_ram_top.v
27
../../rtl/verilog/minsoc_defines.v
28
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
29
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
30
../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
31
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
32
../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
33
../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
34
../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
35
../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
36
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
37
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
38
../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
39
../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
40
../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
41
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
42
../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
43
../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
44
../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
45
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
46
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
47
../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
48
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
49
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
50
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
51
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
52
../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
53
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
54
../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
55
../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
56
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
57
../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
58
../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
59
../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
60
../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
61
../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
62
../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
63
../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
64
../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
65
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
66
../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
67
../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
68
../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
69
../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
70
../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
71
../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
72
../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
73
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
74
../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
75
../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
76
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
77
../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
78
../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
79
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
80
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
81
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
82
../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
83
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
84
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
85
../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
86 2 rfajardo
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
87 31 rfajardo
../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
88
../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
89
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
90
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v
91
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
92
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
93
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
94
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
95
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
96
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
97
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
98
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
99
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
100 2 rfajardo
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
101 31 rfajardo
../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
102 2 rfajardo
../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
103 31 rfajardo
../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
104
../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
105
../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
106
../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
107
../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
108
../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
109
../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
110
../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
111
../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
112
../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
113 2 rfajardo
../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
114 31 rfajardo
../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
115
../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
116
../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
117
../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
118
../../rtl/verilog/ethmac/rtl/verilog/eth_top.v
119
../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
120
../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
121
../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
122
../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
123
../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
124
../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
125
../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
126
../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v
127
../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
128
../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
129
../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
130
../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
131
../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
132
../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
133
../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
134
../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
135
../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
136 2 rfajardo
../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
137
../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
138
../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v

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