OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit_eth/] [spartan3e_starter_kit_eth.ucf] - Blame information for rev 69

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 69 rfajardo
#
2
# Soldered 50MHz clock.
3
#
4
NET "clk" LOC = "C9";
5
 
6
#
7
# Use button "south" as reset.
8
#
9
NET "reset" LOC = "K17" | PULLDOWN ;
10
 
11
#
12
# UART serial port (RS232 DCE) - connector DB9 female.
13
#
14
NET "uart_srx" LOC = "R7";
15
NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ;
16
 
17
###########################
18
##
19
## ETH
20
##
21
NET "eth_txd(3)" LOC = "t5";
22
NET "eth_txd(2)" LOC = "r5";
23
NET "eth_txd(1)" LOC = "t15";
24
NET "eth_txd(0)" LOC = "r11";
25
 
26
NET "eth_tx_en" LOC = "p15";
27
NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE;
28
NET "eth_tx_er" LOC = "r6";
29
 
30
NET "eth_rxd(3)" LOC = "v14";
31
NET "eth_rxd(2)" LOC = "u11";
32
NET "eth_rxd(1)" LOC = "t11";
33
NET "eth_rxd(0)" LOC = "v8";
34
 
35
NET "eth_rx_er" LOC = "u14";
36
NET "eth_rx_dv" LOC = "v2";
37
 
38
NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE;
39
 
40
NET "eth_mdio" LOC = "u5" | PULLUP;
41
NET "eth_crs" LOC = "u13";
42
NET "eth_col" LOC = "u6";
43
NET "eth_mdc" LOC = "p9";
44
 
45
NET "eth_trste" LOC = "p13";                    #put it to a non connected FPGA pin (starter kit schematic BANK3)
46
 
47
NET "eth_fds_mdint" LOC = "r13" | PULLUP;       #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts)
48
###########################
49
 
50
#
51
# JTAG signals - on J4 6-pin accessory header.
52
#
53
 
54
#NET "jtag_tms"  LOC = "D7" | PULLDOWN ;
55
#NET "jtag_tdi"  LOC = "C7" | PULLDOWN ;
56
#NET "jtag_tdo"  LOC = "F8" | SLEW = FAST | DRIVE = 8 ;
57
#NET "jtag_tck"  LOC = "E8" | PULLDOWN ;
58
 
59
#net "jtag_gnd" loc = "k2";                     #put it to a non connected FPGA pin (starter kit schematic BANK3)
60
#net "jtag_vref" loc = "k7";                    #put it to a non connected FPGA pin (starter kit schematic BANK3)
61
 
62
#
63
# End of file.
64
#

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.