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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_bench.v] - Blame information for rev 149

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1 133 rfajardo
`include "minsoc_bench_defines.v"
2
`include "minsoc_defines.v"
3
`include "or1200_defines.v"
4
 
5
`include "timescale.v"
6
 
7
module minsoc_bench();
8
 
9
`ifdef POSITIVE_RESET
10
    localparam RESET_LEVEL = 1'b1;
11
`elsif NEGATIVE_RESET
12
    localparam RESET_LEVEL = 1'b0;
13
`else
14
    localparam RESET_LEVEL = 1'b1;
15
`endif
16
 
17
reg clock, reset;
18
 
19
//Debug interface
20
wire dbg_tms_i;
21
wire dbg_tck_i;
22
wire dbg_tdi_i;
23
wire dbg_tdo_o;
24
wire jtag_vref;
25
wire jtag_gnd;
26
 
27
//SPI wires
28
wire spi_mosi;
29
reg spi_miso;
30
wire spi_sclk;
31
wire [1:0] spi_ss;
32
 
33
//UART wires
34
wire uart_stx;
35
reg uart_srx;
36
 
37
//ETH wires
38
reg eth_col;
39
reg eth_crs;
40
wire eth_trst;
41
reg eth_tx_clk;
42
wire eth_tx_en;
43
wire eth_tx_er;
44
wire [3:0] eth_txd;
45
reg eth_rx_clk;
46
reg eth_rx_dv;
47
reg eth_rx_er;
48
reg [3:0] eth_rxd;
49
reg eth_fds_mdint;
50
wire eth_mdc;
51
wire eth_mdio;
52
 
53
//
54
//      TASKS registers to communicate with interfaces
55
//
56
reg design_ready;
57
reg uart_echo;
58
`ifdef UART
59
reg [40*8-1:0] line;
60
reg [12*8-1:0] hello;
61
reg new_line;
62
reg new_char;
63 149 rfajardo
reg flush_line;
64 133 rfajardo
`endif
65
`ifdef ETHERNET
66
reg [7:0] eth_rx_data [0:1535];            //receive buffer ETH (max packet 1536)
67
reg [7:0] eth_tx_data [0:1535];     //send buffer ETH (max packet 1536)
68
localparam ETH_HDR = 14;
69
localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
70
`endif
71
 
72
 
73
//
74
// Testbench mechanics
75
//
76
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
77
integer initialize, ptr;
78
reg [8*64:0] file_name;
79
integer      firmware_size;  // Note that the .hex file size is greater than this, as each byte in the file needs 2 hex characters.
80
integer      firmware_size_in_header;
81
reg load_file;
82
 
83
initial begin
84
    reset = ~RESET_LEVEL;
85
    clock = 1'b0;
86
        eth_tx_clk = 1'b0;
87
        eth_rx_clk = 1'b0;
88
 
89
    design_ready = 1'b0;
90
    uart_echo = 1'b1;
91
 
92
`ifndef NO_CLOCK_DIVISION
93
    minsoc_top_0.clk_adjust.clk_int = 1'b0;
94
    minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;
95
`endif
96
 
97
    uart_srx = 1'b1;
98
 
99
        eth_col = 1'b0;
100
        eth_crs = 1'b0;
101
        eth_fds_mdint = 1'b1;
102
        eth_rx_er = 1'b0;
103
        eth_rxd = 4'h0;
104
        eth_rx_dv = 1'b0;
105
 
106
 
107
//dual and two port rams from FPGA memory instances have to be initialized to 0
108
    init_fpga_memory();
109
 
110
        load_file = 1'b0;
111
`ifdef INITIALIZE_MEMORY_MODEL
112
        load_file = 1'b1;
113
`endif
114
`ifdef START_UP
115
        load_file = 1'b1;
116
`endif
117
 
118
        //get firmware hex file from command line input
119
        if ( load_file ) begin
120
                if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
121
                        $display("ERROR: Please specify the name of the firmware file to load on start-up.");
122
                        $finish;
123
                end
124
 
125
        // We are passing the firmware size separately as a command-line argument in order
126
        // to avoid this kind of Icarus Verilog warnings:
127
        //   WARNING: minsoc_bench_core.v:111: $readmemh: Standard inconsistency, following 1364-2005.
128
        //   WARNING: minsoc_bench_core.v:111: $readmemh(../../sw/uart/uart.hex): Not enough words in the file for the requested range [0:32767].
129
        // Apparently, some of the $readmemh() warnigns are even required by the standard. The trouble is,
130
        // Verilog's $fread() is not widely implemented in the simulators, so from Verilog alone
131
        // it's not easy to read the firmware file header without getting such warnings.
132
                if ( ! $value$plusargs("firmware_size=%d", firmware_size) ) begin
133
                        $display("ERROR: Please specify the size of the firmware (in bytes) contained in the hex firmware file.");
134
                        $finish;
135
                end
136
 
137
                $readmemh(file_name, program_mem, 0, firmware_size - 1);
138
 
139
                firmware_size_in_header = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };
140
 
141
        if ( firmware_size != firmware_size_in_header ) begin
142
                        $display("ERROR: The firmware size in the file header does not match the firmware size given as command-line argument. Did you forget bin2hex's -size_word flag when generating the firmware file?");
143
                        $finish;
144
        end
145
 
146
        end
147
 
148
`ifdef INITIALIZE_MEMORY_MODEL
149
        // Initialize memory with firmware
150
        initialize = 0;
151
        while ( initialize < firmware_size ) begin
152
                minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];
153
                minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];
154
                minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];
155
                minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];
156
        initialize = initialize + 4;
157
        end
158
        $display("Memory model initialized with firmware:");
159
        $display("%s", file_name);
160
        $display("%d Bytes loaded from %d ...", initialize , firmware_size);
161
`endif
162
 
163
    // Reset controller
164
    repeat (2) @ (negedge clock);
165
    reset = RESET_LEVEL;
166
    repeat (16) @ (negedge clock);
167
    reset = ~RESET_LEVEL;
168
 
169
`ifdef START_UP
170
        // Pass firmware over spi to or1k_startup
171
        ptr = 0;
172
        //read dummy
173
        send_spi(program_mem[ptr]);
174
        send_spi(program_mem[ptr]);
175
        send_spi(program_mem[ptr]);
176
        send_spi(program_mem[ptr]);
177
        //~read dummy
178
        while ( ptr < firmware_size ) begin
179
                send_spi(program_mem[ptr]);
180
                ptr = ptr + 1;
181
        end
182
        $display("Memory start-up completed...");
183
        $display("Loaded firmware:");
184
        $display("%s", file_name);
185
`endif
186
 
187
 
188
        //
189
    // Testbench START
190
        //
191
    design_ready = 1'b1;
192
    $display("Running simulation: if you want to stop it, type ctrl+c and type in finish afterwards.");
193
    fork
194
        begin
195
`ifdef UART
196
 
197
`ifdef ETHERNET
198
`ifdef TEST_ETHERNET
199
            $display("Testing Ethernet firmware, this takes long (~15 min. @ 2.53 GHz dual-core)...");
200
            $display("Ethernet firmware encloses UART firmware, testing UART firmware first...");
201
            test_uart();
202
            test_eth();
203
            $display("Stopping simulation.");
204
            $finish;
205
`endif
206
`endif
207
 
208
`ifdef TEST_UART
209
            $display("Testing UART firmware, this takes a while (~1 min. @ 2.53 GHz dual-core)...");
210
            test_uart();
211
            $display("Stopping simulation.");
212
            $finish;
213
`endif
214
 
215
`endif
216
        end
217
        begin
218
`ifdef ETHERNET
219
`ifdef TEST_ETHERNET
220
            get_mac();
221
            if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 )
222
                $display("Ethernet firmware started correctly.");
223
`endif
224
`endif
225
        end
226
    join
227
 
228
end
229
 
230
 
231
//
232
// Modules instantiations
233
//
234
minsoc_top minsoc_top_0(
235
   .clk(clock),
236
   .reset(reset)
237
 
238
   //JTAG ports
239
`ifdef GENERIC_TAP
240
   , .jtag_tdi(dbg_tdi_i),
241
   .jtag_tms(dbg_tms_i),
242
   .jtag_tck(dbg_tck_i),
243
   .jtag_tdo(dbg_tdo_o),
244
   .jtag_vref(jtag_vref),
245
   .jtag_gnd(jtag_gnd)
246
`endif
247
 
248
   //SPI ports
249
`ifdef START_UP
250
   , .spi_flash_mosi(spi_mosi),
251
   .spi_flash_miso(spi_miso),
252
   .spi_flash_sclk(spi_sclk),
253
   .spi_flash_ss(spi_ss)
254
`endif
255
 
256
   //UART ports
257
`ifdef UART
258
   , .uart_stx(uart_stx),
259
   .uart_srx(uart_srx)
260
`endif // !UART
261
 
262
        // Ethernet ports
263
`ifdef ETHERNET
264
        , .eth_col(eth_col),
265
    .eth_crs(eth_crs),
266
    .eth_trste(eth_trst),
267
    .eth_tx_clk(eth_tx_clk),
268
        .eth_tx_en(eth_tx_en),
269
    .eth_tx_er(eth_tx_er),
270
    .eth_txd(eth_txd),
271
    .eth_rx_clk(eth_rx_clk),
272
        .eth_rx_dv(eth_rx_dv),
273
    .eth_rx_er(eth_rx_er),
274
    .eth_rxd(eth_rxd),
275
    .eth_fds_mdint(eth_fds_mdint),
276
        .eth_mdc(eth_mdc),
277
    .eth_mdio(eth_mdio)
278
`endif // !ETHERNET
279
);
280
 
281
`ifdef VPI_DEBUG
282
        dbg_comm_vpi dbg_if(
283
                .SYS_CLK(clock),
284
                .P_TMS(dbg_tms_i),
285
                .P_TCK(dbg_tck_i),
286
                .P_TRST(),
287
                .P_TDI(dbg_tdi_i),
288
                .P_TDO(dbg_tdo_o)
289
        );
290
`else
291
   assign dbg_tdi_i = 1;
292
   assign dbg_tck_i = 0;
293
   assign dbg_tms_i = 1;
294
`endif
295
 
296
 
297
//
298
// Firmware testers
299
//
300
`ifdef UART
301
task test_uart();
302
    begin
303
            @ (posedge new_line);
304
            $display("UART data received.");
305
            hello = line[12*8-1:0];
306
            //sending character A to UART, B expected
307
            $display("Testing UART interrupt...");
308
            uart_echo = 1'b0;
309
            uart_send(8'h41);       //Character A
310
            @ (posedge new_char);
311
            if ( line[7:0] == "B" )
312
                $display("UART interrupt working.");
313
            else
314 149 rfajardo
                $display("UART interrupt failed. B was expected, %c was received.", line[7:0]);
315 133 rfajardo
            uart_echo = 1'b1;
316
 
317
            if ( hello == "Hello World." )
318
                $display("UART firmware test completed, behaving correctly.");
319
            else
320
                $display("UART firmware test completed, failed.");
321
    end
322
endtask
323
`endif
324
 
325
`ifdef ETHERNET
326
task test_eth();
327
    begin
328
                eth_tx_data[ETH_HDR+0] = 8'hBA;
329
                eth_tx_data[ETH_HDR+1] = 8'h87;
330
                eth_tx_data[ETH_HDR+2] = 8'hAA;
331
                eth_tx_data[ETH_HDR+3] = 8'hBB;
332
                eth_tx_data[ETH_HDR+4] = 8'hCC;
333
                eth_tx_data[ETH_HDR+5] = 8'hDD;
334
 
335
            $display("Sending an Ethernet package to the system and waiting for the data to be output through UART...");
336
                send_mac(6);
337
            repeat(3+40) @ (posedge new_line);
338
            $display("Ethernet test completed.");
339
    end
340
endtask
341
`endif
342
 
343
 
344
//
345
//      Regular clocking and output
346
//
347
always begin
348
    #((`CLK_PERIOD)/2) clock <= ~clock;
349
end
350
 
351 149 rfajardo
`ifdef WAVEFORM_OUTPUT
352 133 rfajardo
initial begin
353 149 rfajardo
        $dumpfile("../results/minsoc_wave.lxt2");
354 133 rfajardo
        $dumpvars();
355
end
356
`endif
357
 
358
 
359
//
360
//      Functionalities tasks: SPI Startup and UART Monitor
361
//
362
//SPI START_UP
363
`ifdef START_UP
364
task send_spi;
365
    input [7:0] data_in;
366
    integer i;
367
    begin
368
        i = 7;
369
        for ( i = 7 ; i >= 0; i = i - 1 ) begin
370
                spi_miso = data_in[i];
371
                        @ (posedge spi_sclk);
372
            end
373
    end
374
endtask
375
`endif
376
//~SPI START_UP
377
 
378
//UART
379
`ifdef UART
380
localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE);
381
 
382
task uart_send;
383
    input [7:0] data;
384
    integer i;
385
    begin
386
        uart_srx = 1'b0;
387
        #UART_TX_WAIT;
388
        for ( i = 0; i < 8 ; i = i + 1 ) begin
389
                    uart_srx = data[i];
390
            #UART_TX_WAIT;
391
            end
392
        uart_srx = 1'b0;
393
        #UART_TX_WAIT;
394
            uart_srx = 1'b1;
395
    end
396
endtask
397
 
398
//UART Monitor (prints uart output on the terminal)
399
// Something to trigger the task
400
initial
401
begin
402
    new_line = 1'b0;
403
    new_char = 1'b0;
404 149 rfajardo
    flush_line = 1'b0;
405 133 rfajardo
end
406
 
407
always @ (posedge clock)
408
    if ( design_ready )
409
        uart_decoder;
410
 
411
task uart_decoder;
412
        integer i;
413
        reg [7:0] tx_byte;
414
        begin
415
        new_char = 1'b0;
416 149 rfajardo
        new_line = 1'b0;
417 133 rfajardo
        // Wait for start bit
418
        while (uart_stx == 1'b1)
419
        @(uart_stx);
420
 
421
        #(UART_TX_WAIT + (UART_TX_WAIT/2));
422
 
423
        for ( i = 0; i < 8 ; i = i + 1 ) begin
424
            tx_byte[i] = uart_stx;
425
            #UART_TX_WAIT;
426
        end
427
 
428
        //Check for stop bit
429
        if (uart_stx == 1'b0) begin
430
            //$display("* WARNING: user stop bit not received when expected at time %d__", $time);
431
            // Wait for return to idle
432
            while (uart_stx == 1'b0)
433
            @(uart_stx);
434
            //$display("* USER UART returned to idle at time %d",$time);
435
        end
436
        // display the char
437
        if ( uart_echo )
438
            $write("%c", tx_byte);
439 149 rfajardo
        if ( flush_line ) begin
440 133 rfajardo
            line = "";
441 149 rfajardo
            flush_line = 1'b0;
442
        end
443
        if ( tx_byte == "\n" ) begin
444 133 rfajardo
            new_line = 1'b1;
445 149 rfajardo
            flush_line = 1'b1;
446
        end
447 133 rfajardo
        else begin
448
            line = { line[39*8-1:0], tx_byte};
449 149 rfajardo
            new_char = 1'b1;
450 133 rfajardo
        end
451
    end
452
endtask
453
//~UART Monitor
454
`endif // !UART
455
//~UART
456
 
457
 
458
//
459
//      TASKS to communicate with interfaces
460
//
461
//MAC_DATA
462
//
463
`ifdef ETHERNET
464
reg [31:0] crc32_result;
465
 
466
task get_mac;
467
    integer conta;
468
    reg LSB;
469
    begin
470
        conta = 0;
471
        LSB = 1;
472
        @ ( posedge eth_tx_en);
473
 
474
        repeat (16) @ (negedge eth_tx_clk);  //8 bytes, preamble (7 bytes) + start of frame (1 byte)
475
 
476
        while ( eth_tx_en == 1'b1 ) begin
477
            @ (negedge eth_tx_clk) begin
478
                if ( LSB == 1'b1 )
479
                    eth_rx_data[conta][3:0] = eth_txd;
480
                else begin
481
                    eth_rx_data[conta][7:4] = eth_txd;
482
                    conta = conta + 1;
483
                end
484
                LSB = ~LSB;
485
            end
486
        end
487
    end
488
endtask
489
 
490
task send_mac;              //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
491
    input [31:0] length;    //ETH_PAYLOAD_MAX_LENGTH 1518
492
    integer conta;
493
    begin
494
        if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin
495
            //DEST MAC
496
            eth_tx_data[0] = 8'h55;
497
            eth_tx_data[1] = 8'h47;
498
            eth_tx_data[2] = 8'h34;
499
            eth_tx_data[3] = 8'h22;
500
            eth_tx_data[4] = 8'h88;
501
            eth_tx_data[5] = 8'h92;
502
 
503
            //SOURCE MAC
504
            eth_tx_data[6] = 8'h3D;
505
            eth_tx_data[7] = 8'h4F;
506
            eth_tx_data[8] = 8'h1A;
507
            eth_tx_data[9] = 8'hBE;
508
            eth_tx_data[10] = 8'h68;
509
            eth_tx_data[11] = 8'h72;
510
 
511
            //LEN
512
            eth_tx_data[12] = length[7:4];
513
            eth_tx_data[13] = length[3:0];
514
 
515
            //DATA input by task caller
516
 
517
            //PAD
518
            for ( conta = length+14; conta < 60; conta = conta + 1 ) begin
519
                eth_tx_data[conta] = 8'h00;
520
            end
521
 
522
            gencrc32(conta);
523
 
524
            eth_tx_data[conta] = crc32_result[31:24];
525
            eth_tx_data[conta+1] = crc32_result[23:16];
526
            eth_tx_data[conta+2] = crc32_result[15:8];
527
            eth_tx_data[conta+3] = crc32_result[7:0];
528
 
529
            send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 );
530
        end
531
        else
532
            $display("Warning: Ethernet packet is to big to be sent.");
533
    end
534
 
535
endtask
536
 
537
task send_rx_packet;
538
  input  [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
539
  input   [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7 
540
  input   [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
541
  input  [31:0] start_addr; // start address
542
  input  [31:0] len; // length of frame in Bytes (without preamble and SFD)
543
  input         plus_drible_nibble; // if length is longer for one nibble
544
  integer       rx_cnt;
545
  reg    [31:0] eth_tx_data_addr_in; // address for reading from RX memory       
546
  reg     [7:0] eth_tx_data_data_out; // data for reading from RX memory
547
begin
548
      @(posedge eth_rx_clk);
549
       eth_rx_dv = 1;
550
 
551
      // set initial rx memory address
552
      eth_tx_data_addr_in = start_addr;
553
 
554
      // send preamble
555
      for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
556
      begin
557
         eth_rxd = preamble_data[3:0];
558
         preamble_data = preamble_data >> 4;
559
        @(posedge eth_rx_clk);
560
      end
561
 
562
      // send SFD
563
      for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
564
      begin
565
         eth_rxd = sfd_data[3:0];
566
         sfd_data = sfd_data >> 4;
567
        @(posedge eth_rx_clk);
568
      end
569
 
570
      // send packet's addresses, type/length, data and FCS
571
      for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
572
      begin
573
        eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
574
        eth_rxd = eth_tx_data_data_out[3:0];
575
        @(posedge eth_rx_clk);
576
        eth_rxd = eth_tx_data_data_out[7:4];
577
        eth_tx_data_addr_in = eth_tx_data_addr_in + 1;
578
        @(posedge eth_rx_clk);
579
      end
580
      if (plus_drible_nibble)
581
      begin
582
        eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
583
        eth_rxd = eth_tx_data_data_out[3:0];
584
        @(posedge eth_rx_clk);
585
      end
586
 
587
       eth_rx_dv = 0;
588
      @(posedge eth_rx_clk);
589
 
590
end
591
endtask // send_rx_packet
592
 
593
//CRC32
594
localparam [31:0] CRC32_POLY = 32'h04C11DB7;
595
 
596
task gencrc32;
597
    input [31:0] crc32_length;
598
 
599
    integer     byte, bit;
600
    reg         msb;
601
    reg [7:0]    current_byte;
602
    reg [31:0]   temp;
603
 
604
    begin
605
        crc32_result = 32'hffffffff;
606
        for (byte = 0; byte < crc32_length; byte = byte + 1) begin
607
            current_byte = eth_tx_data[byte];
608
            for (bit = 0; bit < 8; bit = bit + 1) begin
609
                msb = crc32_result[31];
610
                crc32_result = crc32_result << 1;
611
                if (msb != current_byte[bit]) begin
612
                    crc32_result = crc32_result ^ CRC32_POLY;
613
                    crc32_result[0] = 1;
614
                end
615
            end
616
        end
617
 
618
        // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
619
        //
620
        // Mirror:
621
        for (bit = 0; bit < 32; bit = bit + 1)
622
            temp[31-bit] = crc32_result[bit];
623
 
624
        // Swap and Complement:
625
        crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
626
    end
627
endtask
628
//~CRC32
629
 
630
`endif // !ETHERNET
631
//~MAC_DATA
632
 
633
//Generate tx and rx clocks
634
always begin
635
        #((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
636
end
637
always begin
638
        #((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
639
end
640
//~Generate tx and rx clocks
641
 
642
 
643
 
644
//
645
// TASK to initialize instantiated FPGA dual and two port memory to 0
646
//
647
task init_fpga_memory;
648
    integer i;
649
    begin
650
`ifdef OR1200_RFRAM_TWOPORT
651
`ifdef OR1200_XILINX_RAMB4
652
    for ( i = 0; i < (1<<8); i = i + 1 ) begin
653
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_0.mem[i] = 16'h0000;
654
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_1.mem[i] = 16'h0000;
655
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_0.mem[i] = 16'h0000;
656
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_1.mem[i] = 16'h0000;
657
    end
658
`elsif OR1200_XILINX_RAMB16
659
    for ( i = 0; i < (1<<9); i = i + 1 ) begin
660
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
661
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
662
    end
663
`elsif OR1200_ALTERA_LPM
664
`ifndef OR1200_ALTERA_LPM_XXX
665
    $display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
666
    $display("It uses GENERIC memory instead.");
667
    $display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
668
`endif
669
`ifdef OR1200_ALTERA_LPM_XXX
670
    $display("...Using ALTERA memory for TWOPORT RFRAM!");
671
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
672
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
673
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
674
    end
675
`else
676
    $display("...Using GENERIC memory!");
677
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
678
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
679
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
680
    end
681
`endif
682
`elsif OR1200_XILINX_RAM32X1D
683
    $display("Definition OR1200_XILINX_RAM32X1D in or1200_defines.v does not enable FPGA memory for TWO port RFRAM");
684
    $display("It uses GENERIC memory instead.");
685
    $display("FPGA memory can be used if you choose OR1200_RFRAM_DUALPORT");
686
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
687
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
688
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
689
    end
690
`else
691
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
692
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
693
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
694
    end
695
`endif
696
`elsif OR1200_RFRAM_DUALPORT
697
`ifdef OR1200_XILINX_RAMB4
698
    for ( i = 0; i < (1<<8); i = i + 1 ) begin
699
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[i] = 16'h0000;
700
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[i] = 16'h0000;
701
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_0.mem[i] = 16'h0000;
702
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_1.mem[i] = 16'h0000;
703
    end
704
`elsif OR1200_XILINX_RAMB16
705
    for ( i = 0; i < (1<<9); i = i + 1 ) begin
706
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
707
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
708
    end
709
`elsif OR1200_ALTERA_LPM
710
`ifndef OR1200_ALTERA_LPM_XXX
711
    $display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
712
    $display("It uses GENERIC memory instead.");
713
    $display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
714
`endif
715
`ifdef OR1200_ALTERA_LPM_XXX
716
    $display("...Using ALTERA memory for DUALPORT RFRAM!");
717
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
718
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
719
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
720
    end
721
`else
722
    $display("...Using GENERIC memory!");
723
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
724
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
725
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
726
    end
727
`endif
728
`elsif OR1200_XILINX_RAM32X1D
729
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
730
    for ( i = 0; i < (1<<4); i = i + 1 ) begin
731
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
732
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
733
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
734
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
735
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
736
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
737
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
738
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
739
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
740
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
741
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
742
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
743
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
744
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
745
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
746
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
747
 
748
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
749
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
750
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
751
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
752
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
753
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
754
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
755
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
756
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
757
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
758
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
759
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
760
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
761
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
762
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
763
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
764
 
765
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
766
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
767
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
768
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
769
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
770
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
771
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
772
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
773
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
774
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
775
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
776
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
777
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
778
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
779
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
780
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
781
 
782
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
783
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
784
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
785
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
786
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
787
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
788
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
789
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
790
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
791
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
792
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
793
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
794
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
795
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
796
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
797
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
798
 
799
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
800
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
801
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
802
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
803
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
804
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
805
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
806
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
807
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
808
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
809
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
810
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
811
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
812
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
813
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
814
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
815
 
816
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
817
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
818
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
819
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
820
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
821
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
822
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
823
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
824
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
825
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
826
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
827
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
828
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
829
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
830
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
831
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
832
 
833
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
834
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
835
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
836
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
837
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
838
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
839
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
840
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
841
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
842
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
843
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
844
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
845
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
846
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
847
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
848
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
849
 
850
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
851
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
852
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
853
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
854
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
855
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
856
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
857
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
858
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
859
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
860
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
861
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
862
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
863
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
864
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
865
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
866
    end
867
`else
868
    for ( i = 0; i < (1<<4); i = i + 1 ) begin
869
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
870
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
871
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
872
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
873
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
874
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
875
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
876
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
877
 
878
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
879
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
880
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
881
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
882
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
883
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
884
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
885
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
886
 
887
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
888
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
889
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
890
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
891
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
892
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
893
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
894
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
895
 
896
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
897
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
898
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
899
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
900
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
901
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
902
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
903
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
904
 
905
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
906
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
907
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
908
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
909
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
910
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
911
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
912
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
913
 
914
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
915
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
916
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
917
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
918
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
919
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
920
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
921
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
922
 
923
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
924
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
925
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
926
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
927
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
928
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
929
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
930
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
931
 
932
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
933
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
934
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
935
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
936
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
937
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
938
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
939
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
940
    end
941
`endif
942
`else
943
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
944
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
945
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
946
    end
947
`endif
948
`endif
949
    end
950
endtask
951
 
952
endmodule
953
 

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