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[/] [minsoc/] [trunk/] [prj/] [src/] [blackboxes/] [ethmac.v] - Blame information for rev 85

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`include "ethmac_defines.v"
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module ethmac
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(
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  // WISHBONE common
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  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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  // WISHBONE slave
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  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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  // WISHBONE master
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  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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`ifdef ETH_WISHBONE_B3
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  m_wb_cti_o, m_wb_bte_o,
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`endif
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  //TX
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  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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  //RX
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  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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  // MIIM
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  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
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  int_o
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  // Bist
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`ifdef ETH_BIST
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  ,
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  // debug chain signals
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  mbist_si_i,       // bist scan serial in
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  mbist_so_o,       // bist scan serial out
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  mbist_ctrl_i        // bist chain shift control
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`endif
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);
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parameter Tp = 1;
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// WISHBONE common
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input           wb_clk_i;     // WISHBONE clock
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input           wb_rst_i;     // WISHBONE reset
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input   [31:0]  wb_dat_i;     // WISHBONE data input
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output  [31:0]  wb_dat_o;     // WISHBONE data output
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output          wb_err_o;     // WISHBONE error output
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// WISHBONE slave
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input   [11:2]  wb_adr_i;     // WISHBONE address input
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input    [3:0]  wb_sel_i;     // WISHBONE byte select input
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input           wb_we_i;      // WISHBONE write enable input
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input           wb_cyc_i;     // WISHBONE cycle input
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input           wb_stb_i;     // WISHBONE strobe input
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output          wb_ack_o;     // WISHBONE acknowledge output
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// WISHBONE master
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output  [31:0]  m_wb_adr_o;
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output   [3:0]  m_wb_sel_o;
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output          m_wb_we_o;
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input   [31:0]  m_wb_dat_i;
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output  [31:0]  m_wb_dat_o;
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output          m_wb_cyc_o;
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output          m_wb_stb_o;
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input           m_wb_ack_i;
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input           m_wb_err_i;
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wire    [29:0]  m_wb_adr_tmp;
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`ifdef ETH_WISHBONE_B3
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output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
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output   [1:0]  m_wb_bte_o;   // Burst Type Extension
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`endif
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// Tx
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input           mtx_clk_pad_i; // Transmit clock (from PHY)
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output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
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output          mtxen_pad_o;   // Transmit enable (to PHY)
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output          mtxerr_pad_o;  // Transmit error (to PHY)
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// Rx
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input           mrx_clk_pad_i; // Receive clock (from PHY)
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input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
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input           mrxdv_pad_i;   // Receive data valid (from PHY)
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input           mrxerr_pad_i;  // Receive data error (from PHY)
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// Common Tx and Rx
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input           mcoll_pad_i;   // Collision (from PHY)
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input           mcrs_pad_i;    // Carrier sense (from PHY)
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// MII Management interface
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input           md_pad_i;      // MII data input (from I/O cell)
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output          mdc_pad_o;     // MII Management data clock (to PHY)
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output          md_pad_o;      // MII data output (to I/O cell)
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output          md_padoe_o;    // MII data output enable (to I/O cell)
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output          int_o;         // Interrupt output
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// Bist
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`ifdef ETH_BIST
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input   mbist_si_i;       // bist scan serial in
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output  mbist_so_o;       // bist scan serial out
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input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
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`endif
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endmodule

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