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[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_bench.prj] - Blame information for rev 88

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Line No. Rev Author Line
1 88 rfajardo
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
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PROJECT_SRC=(minsoc_bench_defines.v
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minsoc_bench.v
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minsoc_memory_model.v
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dbg_comm_vpi.v
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fpga_memory_primitives.v
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timescale.v)
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