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[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_top.prj] - Blame information for rev 89

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Line No. Rev Author Line
1 89 rfajardo
PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)
2 85 rfajardo
PROJECT_SRC=(minsoc_defines.v
3
timescale.v
4
minsoc_top.v
5 88 rfajardo
minsoc_tc_top.v
6
minsoc_onchip_ram.v
7
minsoc_onchip_ram_top.v
8
minsoc_clock_manager.v
9
altera_pll.v
10
xilinx_dcm.v
11
minsoc_xilinx_internal_jtag.v
12 85 rfajardo
spi_top.v
13
spi_defines.v
14
spi_shift.v
15
spi_clgen.v
16 88 rfajardo
OR1K_startup_generic.v)
17
 

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