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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Blame information for rev 56

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1 2 rfajardo
 
2
`include "minsoc_defines.v"
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module minsoc_clock_manager(
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        clk_i,
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        clk_o
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);
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// 
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// Parameters 
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// 
12 56 javieralso
   parameter    divisor = 2;
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14 2 rfajardo
input clk_i;
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output clk_o;
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`ifdef NO_CLOCK_DIVISION
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assign clk_o = clk_i;
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`elsif GENERIC_CLOCK_DIVISION
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reg [31:0] clock_divisor;
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reg clk_int;
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always @ (posedge clk_i)
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begin
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        clock_divisor <= clock_divisor + 1'b1;
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        if ( clock_divisor >= divisor/2 - 1 ) begin
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                clk_int <= ~clk_int;
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                clock_divisor <= 32'h0000_0000;
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        end
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end
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assign clk_o = clk_int;
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`elsif FPGA_CLOCK_DIVISION
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34 56 javieralso
 `ifdef ALTERA_FPGA
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    `ifdef ARRIA_GX
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      defparam systemPll.FAMILY = "Arria GX";
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    `elsif ARRIA_II_GX
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      defparam systemPll.FAMILY = "Arria II GX";
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    `elsif CYCLONE_I
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      defparam systemPll.FAMILY = "Cyclone I";
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    `elsif CYCLONE_II
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      defparam systemPll.FAMILY = "Cyclone II";
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    `elsif CYCLONE_III
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      defparam systemPll.FAMILY = "Cyclone III";
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    `elsif CYCLONE_III_LS
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      defparam systemPll.FAMILY = "Cyclone III LS";
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    `elsif CYCLONE_IV_E
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      defparam systemPll.FAMILY = "Cyclone IV E";
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    `elsif CYCLONE_IV_GS
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      defparam systemPll.FAMILY = "Cyclone IV GS";
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    `elsif MAX_II
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      defparam systemPll.FAMILY = "MAX II";
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    `elsif MAX_V
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      defparam systemPll.FAMILY = "MAX V";
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    `elsif MAX3000A
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      defparam systemPll.FAMILY = "MAX3000A";
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    `elsif MAX7000AE
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      defparam systemPll.FAMILY = "MAX7000AE";
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    `elsif MAX7000B
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      defparam systemPll.FAMILY = "MAX7000B";
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    `elsif MAX7000S
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      defparam systemPll.FAMILY = "MAX7000S";
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    `elsif STRATIX
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      defparam systemPll.FAMILY = "Stratix";
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    `elsif STRATIX_II
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      defapram systemPll.FAMILY = "Stratix II";
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    `elsif STRATIX_II_GX
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      defparam systemPll.FAMILY = "Stratix II GX";
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    `elsif STRATIX_III
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      defparam systemPll.FAMILY = "Stratix III"
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    `endif
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    defparam systemPll.FREQ_DIV = divisor;
74 52 javieralso
 
75 56 javieralso
    minsoc_pll systemPll
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      (
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       .inclk0(clk_i),
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       .c0(clk_o)
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      );
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81 2 rfajardo
`elsif XILINX_FPGA
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`ifdef SPARTAN2
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        `define MINSOC_DLL
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`elsif VIRTEX
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        `define MINSOC_DLL
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`endif  // !SPARTAN2/VIRTEX
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`ifdef SPARTAN3
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        `define MINSOC_DCM
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`elsif VIRTEX2
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        `define MINSOC_DCM
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`endif  // !SPARTAN3/VIRTEX2
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`ifdef SPARTAN3E
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        `define MINSOC_DCM_SP
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`elsif SPARTAN3A
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        `define MINSOC_DCM_SP
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`endif  // !SPARTAN3E/SPARTAN3A
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`ifdef VIRTEX4
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        `define MINSOC_DCM_ADV
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        `define MINSOC_DCM_COMPONENT "VIRTEX4"
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`elsif VIRTEX5
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        `define MINSOC_DCM_ADV
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        `define MINSOC_DCM_COMPONENT "VIRTEX5"
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`endif  // !VIRTEX4/VIRTEX5
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wire CLKIN_IN;
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wire CLKDV_OUT;
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assign CLKIN_IN = clk_i;
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assign clk_o = CLKDV_OUT;
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wire CLKIN_IBUFG;
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wire CLK0_BUF;
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wire CLKFB_IN;
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wire CLKDV_BUF;
119
 
120
IBUFG CLKIN_IBUFG_INST (
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        .I(CLKIN_IN),
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        .O(CLKIN_IBUFG)
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);
124
 
125
BUFG CLK0_BUFG_INST (
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        .I(CLK0_BUF),
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        .O(CLKFB_IN)
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);
129
 
130
BUFG CLKDV_BUFG_INST (
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        .I(CLKDV_BUF),
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        .O(CLKDV_OUT)
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);
134
 
135
`ifdef MINSOC_DLL
136
 
137
CLKDLL #(
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        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
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        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
140
        .FACTORY_JF(16'hC080),                  // FACTORY JF Values
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        .STARTUP_WAIT("FALSE")                  // Delay config DONE until DLL LOCK, TRUE/FALSE
142
) CLKDLL_inst (
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        .CLK0(CLK0_BUF),                        // 0 degree DLL CLK output
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        .CLK180(),                              // 180 degree DLL CLK output
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        .CLK270(),                              // 270 degree DLL CLK output
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        .CLK2X(),                               // 2X DLL CLK output
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        .CLK90(),                               // 90 degree DLL CLK output
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        .CLKDV(CLKDV_BUF),                      // Divided DLL CLK out (CLKDV_DIVIDE)
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        .LOCKED(),                              // DLL LOCK status output
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        .CLKFB(CLKFB_IN),                       // DLL clock feedback
151
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DLL)
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        .RST(1'b0)                              // DLL asynchronous reset input
153
);
154
 
155
`elsif MINSOC_DCM
156
 
157
DCM #(
158
        .SIM_MODE("SAFE"),                      // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
159
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
160
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
161
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
162
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
163
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
164
        .CLKIN_PERIOD(0.0),                     // Specify period of input clock
165
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift of NONE, FIXED or VARIABLE
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        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
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        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
168
                                                //   an integer from 0 to 15
169
        .DFS_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for frequency synthesis
170
        .DLL_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for DLL
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        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
172
        .FACTORY_JF(16'hC080),                  // FACTORY JF values
173
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 255
174
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, TRUE/FALSE
175
) DCM_inst (
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        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
177
        .CLK180(),                              // 180 degree DCM CLK output
178
        .CLK270(),                              // 270 degree DCM CLK output
179
        .CLK2X(),                               // 2X DCM CLK output
180
        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
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        .CLK90(),                               // 90 degree DCM CLK output
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        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
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        .CLKFX(),                               // DCM CLK synthesis out (M/D)
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        .CLKFX180(),                            // 180 degree CLK synthesis out
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        .LOCKED(),                              // DCM LOCK status output
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        .PSDONE(),                              // Dynamic phase adjust done output
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        .STATUS(),                              // 8-bit DCM status bits output
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        .CLKFB(CLKFB_IN),                       // DCM clock feedback
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        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
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        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
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        .PSEN(1'b0),                            // Dynamic phase adjust enable input
192
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
193
        .RST(1'b0)                              // DCM asynchronous reset input
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);
195
 
196
`elsif MINSOC_DCM_SP
197
 
198
DCM_SP #(
199
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
200
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
201
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
202
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
203
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
204
        .CLKIN_PERIOD(0.0),                     // Specify period of input clock
205
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift of NONE, FIXED or VARIABLE
206
        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
207
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
208
                                                //   an integer from 0 to 15
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        .DLL_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for DLL
210
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
211
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 255
212
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) DCM_SP_inst (
214
        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
215
        .CLK180(),                              // 180 degree DCM CLK output
216
        .CLK270(),                              // 270 degree DCM CLK output
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        .CLK2X(),                               // 2X DCM CLK output
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        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
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        .CLK90(),                               // 90 degree DCM CLK output
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        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
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        .CLKFX(),                               // DCM CLK synthesis out (M/D)
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        .CLKFX180(),                            // 180 degree CLK synthesis out
223
        .LOCKED(),                              // DCM LOCK status output
224
        .PSDONE(),                              // Dynamic phase adjust done output
225
        .STATUS(),                              // 8-bit DCM status bits output
226
        .CLKFB(CLKFB_IN),                       // DCM clock feedback
227
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
228
        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
229
        .PSEN(1'b0),                            // Dynamic phase adjust enable input
230
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
231
        .RST(1'b0)                              // DCM asynchronous reset input
232
);
233
 
234
`elsif MINSOC_DCM_ADV
235
 
236
DCM_ADV #(
237
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
238
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
239
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
240
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
241
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
242
        .CLKIN_PERIOD(10.0),                    // Specify period of input clock in ns from 1.25 to 1000.00
243
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift mode of NONE, FIXED,
244
                                                // VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
245
        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
246
        .DCM_AUTOCALIBRATION("TRUE"),           // DCM calibration circuitry "TRUE"/"FALSE"
247
        .DCM_PERFORMANCE_MODE("MAX_SPEED"),     // Can be MAX_SPEED or MAX_RANGE
248
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
249
                                                //   an integer from 0 to 15
250
        .DFS_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for frequency synthesis
251
        .DLL_FREQUENCY_MODE("LOW"),             // LOW, HIGH, or HIGH_SER frequency mode for DLL
252
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, "TRUE"/"FALSE"
253
        .FACTORY_JF(16'hf0f0),                  // FACTORY JF value suggested to be set to 16’hf0f0
254
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 1023
255
        .SIM_DEVICE(`MINSOC_DCM_COMPONENT),     // Set target device, "VIRTEX4" or "VIRTEX5"
256
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
257
) DCM_ADV_inst (
258
        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
259
        .CLK180(),                              // 180 degree DCM CLK output
260
        .CLK270(),                              // 270 degree DCM CLK output
261
        .CLK2X(),                               // 2X DCM CLK output
262
        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
263
        .CLK90(),                               // 90 degree DCM CLK output
264
        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
265
        .CLKFX(),                               // DCM CLK synthesis out (M/D)
266
        .CLKFX180(),                            // 180 degree CLK synthesis out
267
        .DO(),                                  // 16-bit data output for Dynamic Reconfiguration Port (DRP)
268
        .DRDY(),                                // Ready output signal from the DRP
269
        .LOCKED(),                              // DCM LOCK status output
270
        .PSDONE(),                              // Dynamic phase adjust done output
271
        .CLKFB(CLKFB_IN),                       // DCM clock feedback
272
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
273
        .DADDR(7'h00),                          // 7-bit address for the DRP
274
        .DCLK(1'b0),                            // Clock for the DRP
275
        .DEN(1'b0),                             // Enable input for the DRP
276
        .DI(16'h0000),                          // 16-bit data input for the DRP
277
        .DWE(1'b0),                             // Active high allows for writing configuration memory
278
        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
279
        .PSEN(1'b0),                            // Dynamic phase adjust enable input
280
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
281
        .RST(1'b0)                              // DCM asynchronous reset input
282
);
283
 
284
`endif  // !MINSOC_DLL/MINSOC_DCM/MINSOC_DCM_SP/MINSOC_DCM_ADV
285
`endif  // !ALTERA_FPGA/XILINX_FPGA
286
`endif  // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
287
 
288
 
289
endmodule

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