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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Blame information for rev 62

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1 2 rfajardo
 
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`include "minsoc_defines.v"
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module minsoc_clock_manager(
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        clk_i,
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        clk_o
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);
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// 
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// Parameters 
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// 
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   parameter    divisor = 2;
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input clk_i;
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output clk_o;
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`ifdef NO_CLOCK_DIVISION
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assign clk_o = clk_i;
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`elsif GENERIC_CLOCK_DIVISION
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reg [31:0] clock_divisor;
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reg clk_int;
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always @ (posedge clk_i)
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begin
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        clock_divisor <= clock_divisor + 1'b1;
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        if ( clock_divisor >= divisor/2 - 1 ) begin
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                clk_int <= ~clk_int;
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                clock_divisor <= 32'h0000_0000;
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        end
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end
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assign clk_o = clk_int;
32 62 rfajardo
 
33 2 rfajardo
`elsif FPGA_CLOCK_DIVISION
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`ifdef ALTERA_FPGA
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altera_pll #
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(
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    .FREQ_DIV(divisor)
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)
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minsoc_altera_pll
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(
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    .inclk0(clk_i),
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    .c0(clk_o)
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);
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45 2 rfajardo
`elsif XILINX_FPGA
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xilinx_dcm #
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(
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    .divisor(divisor)
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)
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minsoc_xilinx_dcm
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(
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    .clk_i(clk_i),
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    .clk_o(clk_o)
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);
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`endif  // !ALTERA_FPGA/XILINX_FPGA
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`endif  // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
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endmodule

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