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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_startup/] [OR1K_startup_generic.v] - Blame information for rev 20

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1 2 rfajardo
 
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`include "minsoc_defines.v"
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module OR1K_startup
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  (
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    input [6:2]       wb_adr_i,
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    input             wb_stb_i,
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    input             wb_cyc_i,
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    output reg [31:0] wb_dat_o,
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    output reg        wb_ack_o,
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    input             wb_clk,
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    input             wb_rst
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   );
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       wb_dat_o <= 32'h15000000;
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     else
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       case (wb_adr_i)
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          1 : wb_dat_o <= 32'hA8200000;
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          2 : wb_dat_o <= { 16'h1880 , `APP_ADDR_SPI , 8'h00 };
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          3 : wb_dat_o <= 32'hA8A00520;
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          4 : wb_dat_o <= 32'hA8600001;
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          5 : wb_dat_o <= 32'h04000014;
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          6 : wb_dat_o <= 32'hD4041818;
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          7 : wb_dat_o <= 32'h04000012;
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          8 : wb_dat_o <= 32'hD4040000;
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          9 : wb_dat_o <= 32'hE0431804;
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         10 : wb_dat_o <= 32'h0400000F;
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         11 : wb_dat_o <= 32'h9C210008;
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         12 : wb_dat_o <= 32'h0400000D;
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         13 : wb_dat_o <= 32'hE1031804;
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         14 : wb_dat_o <= 32'hE4080000;
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         15 : wb_dat_o <= 32'h0FFFFFFB;
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         16 : wb_dat_o <= 32'hD4081800;
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         17 : wb_dat_o <= 32'h04000008;
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         18 : wb_dat_o <= 32'h9C210004;
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         19 : wb_dat_o <= 32'hD4011800;
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         20 : wb_dat_o <= 32'hE4011000;
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         21 : wb_dat_o <= 32'h0FFFFFFC;
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         22 : wb_dat_o <= 32'hA8C00100;
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         23 : wb_dat_o <= 32'h44003000;
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         24 : wb_dat_o <= 32'hD4040018;
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         25 : wb_dat_o <= 32'hD4042810;
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         26 : wb_dat_o <= 32'h84640010;
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         27 : wb_dat_o <= 32'hBC030520;
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         28 : wb_dat_o <= 32'h13FFFFFE;
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         29 : wb_dat_o <= 32'h15000000;
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         30 : wb_dat_o <= 32'h44004800;
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         31 : wb_dat_o <= 32'h84640000;
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       endcase
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       wb_ack_o <= 1'b0;
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     else
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       wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
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endmodule // OR1K_startup

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