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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_startup/] [spi_clgen.v] - Blame information for rev 2

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1 2 rfajardo
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  spi_clgen.v                                                 ////
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////                                                              ////
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////  This file is part of the SPI IP core project                ////
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////  http://www.opencores.org/projects/spi/                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Srot (simons@opencores.org)                     ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2002 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "spi_defines.v"
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`include "timescale.v"
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module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge);
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   parameter divider_len = 2;
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   parameter divider = 1;
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   parameter Tp = 1;
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   input                            clk_in;   // input clock (system clock)
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   input                            rst;      // reset
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   input                            enable;   // clock enable
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   input                            go;       // start transfer
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   input                            last_clk; // last clock
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   //input [spi_divider_len-1:0]     divider;  // clock divider (output clock is divided by this value)
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   output                           clk_out;  // output clock
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   output                           pos_edge; // pulse marking positive edge of clk_out
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   output                           neg_edge; // pulse marking negative edge of clk_out
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   reg                              clk_out;
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   reg                              pos_edge;
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   reg                              neg_edge;
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   reg [divider_len-1:0]             cnt;      // clock counter 
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   wire                             cnt_zero; // conter is equal to zero
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   wire                             cnt_one;  // conter is equal to one
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   assign cnt_zero = cnt == {divider_len{1'b0}};
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   assign cnt_one  = cnt == {{divider_len-1{1'b0}}, 1'b1};
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   // Counter counts half period
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   always @(posedge clk_in or posedge rst)
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     begin
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        if(rst)
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          cnt <= #Tp {divider_len{1'b1}};
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        else
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          begin
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             if(!enable || cnt_zero)
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               cnt <= #Tp divider;
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             else
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               cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1};
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          end
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     end
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   // clk_out is asserted every other half period
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   always @(posedge clk_in or posedge rst)
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     begin
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        if(rst)
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          clk_out <= #Tp 1'b0;
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        else
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          clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
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     end
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   // Pos and neg edge signals
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   always @(posedge clk_in or posedge rst)
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     begin
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        if(rst)
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          begin
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             pos_edge  <= #Tp 1'b0;
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             neg_edge  <= #Tp 1'b0;
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          end
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        else
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          begin
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             pos_edge  <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
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             neg_edge  <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
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          end
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     end
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endmodule

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