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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Blame information for rev 158

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1 2 rfajardo
`include "minsoc_defines.v"
2 158 rfajardo
`include "interconnect_defines.v"
3 2 rfajardo
`include "or1200_defines.v"
4
 
5
module minsoc_top (
6
   clk,reset
7
 
8
   //JTAG ports
9
`ifdef GENERIC_TAP
10
   , jtag_tdi,jtag_tms,jtag_tck,
11
   jtag_tdo,jtag_vref,jtag_gnd
12
`endif
13
 
14
   //SPI ports
15
`ifdef START_UP
16
   , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss
17
`endif
18
 
19
   //UART ports
20
`ifdef UART
21
   , uart_stx,uart_srx
22
`endif
23
 
24
        // Ethernet ports
25
`ifdef ETHERNET
26
        , eth_col, eth_crs, eth_trste, eth_tx_clk,
27
        eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk,
28
        eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint,
29
        eth_mdc, eth_mdio
30
`endif
31
);
32
 
33
//
34
// I/O Ports
35
//
36
 
37
   input         clk;
38
   input         reset;
39
 
40
//
41
// SPI controller external i/f wires
42
//
43
`ifdef START_UP
44
output spi_flash_mosi;
45
input spi_flash_miso;
46
output spi_flash_sclk;
47
output [1:0] spi_flash_ss;
48
`endif
49
 
50
//
51
// UART
52
//
53
`ifdef UART
54
   output        uart_stx;
55
   input         uart_srx;
56
`endif
57
 
58
//
59
// Ethernet
60
//
61
`ifdef ETHERNET
62
output                  eth_tx_er;
63
input                   eth_tx_clk;
64
output                  eth_tx_en;
65
output  [3:0]            eth_txd;
66
input                   eth_rx_er;
67
input                   eth_rx_clk;
68
input                   eth_rx_dv;
69
input   [3:0]            eth_rxd;
70
input                   eth_col;
71
input                   eth_crs;
72
output                  eth_trste;
73
input                   eth_fds_mdint;
74
inout                   eth_mdio;
75
output                  eth_mdc;
76
`endif
77
 
78
//
79
// JTAG
80
//
81
`ifdef GENERIC_TAP
82
   input         jtag_tdi;
83
   input         jtag_tms;
84
   input         jtag_tck;
85
   output        jtag_tdo;
86
   output        jtag_vref;
87
   output        jtag_gnd;
88
 
89
 
90
assign jtag_vref = 1'b1;
91
assign jtag_gnd = 1'b0;
92
`endif
93
 
94
wire rstn;
95
 
96 7 rfajardo
`ifdef POSITIVE_RESET
97 2 rfajardo
assign rstn = ~reset;
98 7 rfajardo
`elsif NEGATIVE_RESET
99
assign rstn = reset;
100
`endif
101 2 rfajardo
 
102
//
103
// Internal wires
104
//
105
 
106
//
107
// Debug core master i/f wires
108
//
109
wire    [31:0]           wb_dm_adr_o;
110
wire    [31:0]           wb_dm_dat_i;
111
wire    [31:0]           wb_dm_dat_o;
112
wire    [3:0]            wb_dm_sel_o;
113
wire                    wb_dm_we_o;
114
wire                    wb_dm_stb_o;
115
wire                    wb_dm_cyc_o;
116
wire                    wb_dm_ack_i;
117
wire                    wb_dm_err_i;
118
 
119
//
120 158 rfajardo
// Debug core JSP slave i/f wires
121
//
122
wire    [31:0]   wb_jsp_dat_i;
123
wire    [31:0]   wb_jsp_dat_o;
124
wire    [31:0]   wb_jsp_adr_i;
125
wire    [3:0]    wb_jsp_sel_i;
126
wire                    wb_jsp_we_i;
127
wire                    wb_jsp_cyc_i;
128
wire                    wb_jsp_stb_i;
129
wire                    wb_jsp_ack_o;
130
wire                    wb_jsp_err_o;
131
 
132
//
133 2 rfajardo
// Debug <-> RISC wires
134
//
135
wire    [3:0]            dbg_lss;
136
wire    [1:0]            dbg_is;
137
wire    [10:0]           dbg_wp;
138
wire                    dbg_bp;
139
wire    [31:0]           dbg_dat_dbg;
140
wire    [31:0]           dbg_dat_risc;
141
wire    [31:0]           dbg_adr;
142
wire                    dbg_ewt;
143
wire                    dbg_stall;
144 20 rfajardo
wire            dbg_we;
145
wire            dbg_stb;
146
wire            dbg_ack;
147 2 rfajardo
 
148
//
149
// RISC instruction master i/f wires
150
//
151
wire    [31:0]           wb_rim_adr_o;
152
wire                    wb_rim_cyc_o;
153
wire    [31:0]           wb_rim_dat_i;
154
wire    [31:0]           wb_rim_dat_o;
155
wire    [3:0]            wb_rim_sel_o;
156
wire                    wb_rim_ack_i;
157
wire                    wb_rim_err_i;
158
wire                    wb_rim_rty_i = 1'b0;
159
wire                    wb_rim_we_o;
160
wire                    wb_rim_stb_o;
161
wire    [31:0]           wb_rif_dat_i;
162
wire                    wb_rif_ack_i;
163
 
164
//
165
// RISC data master i/f wires
166
//
167
wire    [31:0]           wb_rdm_adr_o;
168
wire                    wb_rdm_cyc_o;
169
wire    [31:0]           wb_rdm_dat_i;
170
wire    [31:0]           wb_rdm_dat_o;
171
wire    [3:0]            wb_rdm_sel_o;
172
wire                    wb_rdm_ack_i;
173
wire                    wb_rdm_err_i;
174
wire                    wb_rdm_rty_i = 1'b0;
175
wire                    wb_rdm_we_o;
176
wire                    wb_rdm_stb_o;
177
 
178
//
179
// RISC misc
180
//
181 31 rfajardo
wire    [`OR1200_PIC_INTS-1:0]           pic_ints;
182 2 rfajardo
 
183
//
184
// Flash controller slave i/f wires
185
//
186
wire    [31:0]           wb_fs_dat_i;
187
wire    [31:0]           wb_fs_dat_o;
188
wire    [31:0]           wb_fs_adr_i;
189
wire    [3:0]            wb_fs_sel_i;
190
wire                    wb_fs_we_i;
191
wire                    wb_fs_cyc_i;
192
wire                    wb_fs_stb_i;
193
wire                    wb_fs_ack_o;
194
wire                    wb_fs_err_o;
195
 
196
//
197
// SPI controller slave i/f wires
198
//
199
wire    [31:0]           wb_sp_dat_i;
200
wire    [31:0]           wb_sp_dat_o;
201
wire    [31:0]           wb_sp_adr_i;
202
wire    [3:0]            wb_sp_sel_i;
203
wire                    wb_sp_we_i;
204
wire                    wb_sp_cyc_i;
205
wire                    wb_sp_stb_i;
206
wire                    wb_sp_ack_o;
207
wire                    wb_sp_err_o;
208
 
209
//
210
// SPI controller external i/f wires
211
//
212
wire spi_flash_mosi;
213
wire spi_flash_miso;
214
wire spi_flash_sclk;
215
wire [1:0] spi_flash_ss;
216
 
217
//
218
// SRAM controller slave i/f wires
219
//
220
wire    [31:0]           wb_ss_dat_i;
221
wire    [31:0]           wb_ss_dat_o;
222
wire    [31:0]           wb_ss_adr_i;
223
wire    [3:0]            wb_ss_sel_i;
224
wire                    wb_ss_we_i;
225
wire                    wb_ss_cyc_i;
226
wire                    wb_ss_stb_i;
227
wire                    wb_ss_ack_o;
228
wire                    wb_ss_err_o;
229
 
230
//
231
// Ethernet core master i/f wires
232
//
233
wire    [31:0]           wb_em_adr_o;
234
wire    [31:0]           wb_em_dat_i;
235
wire    [31:0]           wb_em_dat_o;
236
wire    [3:0]            wb_em_sel_o;
237
wire                    wb_em_we_o;
238
wire                    wb_em_stb_o;
239
wire                    wb_em_cyc_o;
240
wire                    wb_em_ack_i;
241
wire                    wb_em_err_i;
242
 
243
//
244
// Ethernet core slave i/f wires
245
//
246
wire    [31:0]           wb_es_dat_i;
247
wire    [31:0]           wb_es_dat_o;
248
wire    [31:0]           wb_es_adr_i;
249
wire    [3:0]            wb_es_sel_i;
250
wire                    wb_es_we_i;
251
wire                    wb_es_cyc_i;
252
wire                    wb_es_stb_i;
253
wire                    wb_es_ack_o;
254
wire                    wb_es_err_o;
255
 
256
//
257
// Ethernet external i/f wires
258
//
259
wire                    eth_mdo;
260
wire                    eth_mdoe;
261
 
262
//
263
// UART16550 core slave i/f wires
264
//
265
wire    [31:0]           wb_us_dat_i;
266
wire    [31:0]           wb_us_dat_o;
267
wire    [31:0]           wb_us_adr_i;
268
wire    [3:0]            wb_us_sel_i;
269
wire                    wb_us_we_i;
270
wire                    wb_us_cyc_i;
271
wire                    wb_us_stb_i;
272
wire                    wb_us_ack_o;
273
wire                    wb_us_err_o;
274
 
275
//
276
// UART external i/f wires
277
//
278
wire                    uart_stx;
279
wire                    uart_srx;
280
 
281
//
282
// Reset debounce
283
//
284
reg                     rst_r;
285
reg                     wb_rst;
286
 
287
//
288
// Global clock
289
//
290
wire                    wb_clk;
291
 
292
//
293
// Reset debounce
294
//
295
always @(posedge wb_clk or negedge rstn)
296
        if (~rstn)
297
                rst_r <= 1'b1;
298
        else
299
                rst_r <= #1 1'b0;
300
 
301
//
302
// Reset debounce
303
//
304
always @(posedge wb_clk)
305
        wb_rst <= #1 rst_r;
306
 
307
//
308 7 rfajardo
// Clock Divider
309 2 rfajardo
//
310
minsoc_clock_manager #
311
(
312 56 javieralso
   .divisor(`CLOCK_DIVISOR)
313 2 rfajardo
)
314
clk_adjust (
315
        .clk_i(clk),
316
        .clk_o(wb_clk)
317
);
318
 
319
//
320
// Unused interrupts
321
//
322
assign pic_ints[`APP_INT_RES1] = 'b0;
323
assign pic_ints[`APP_INT_RES2] = 'b0;
324
assign pic_ints[`APP_INT_RES3] = 'b0;
325
assign pic_ints[`APP_INT_PS2] = 'b0;
326
 
327
//
328
// Ethernet tri-state
329
//
330
`ifdef ETHERNET
331
assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz;
332
assign eth_trste = `ETH_RESET;
333
`endif
334
 
335
 
336
//
337
// RISC Instruction address for Flash
338
//
339
// Until first access to real Flash area,
340
// CPU instruction is fixed to jump to the Flash area.
341
// After Flash area is accessed, CPU instructions 
342
// come from the tc_top (wishbone "switch").
343
//
344
`ifdef START_UP
345
reg jump_flash;
346
reg [3:0] rif_counter;
347
reg [31:0] rif_dat_int;
348
reg rif_ack_int;
349
 
350
always @(posedge wb_clk or negedge rstn)
351
begin
352
        if (!rstn) begin
353
                jump_flash <= #1 1'b1;
354
                rif_counter <= 4'h0;
355
                rif_ack_int <= 1'b0;
356
        end
357
        else begin
358
                rif_ack_int <= 1'b0;
359
 
360
                if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
361
                        jump_flash <= #1 1'b0;
362
 
363
                if ( jump_flash == 1'b1 ) begin
364 33 rfajardo
                        if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o )
365
                                rif_ack_int <= 1'b1;
366
 
367
            if ( rif_ack_int == 1'b1 ) begin
368 2 rfajardo
                                rif_counter <= rif_counter + 1'b1;
369 33 rfajardo
                                rif_ack_int <= 1'b0;
370
            end
371 2 rfajardo
                end
372
        end
373
end
374
 
375
always @ (rif_counter)
376
begin
377
        case ( rif_counter )
378
                4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 };
379
                4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 };
380
                4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 };
381
                4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 };
382
                default: rif_dat_int = 32'h0000_0000;
383
        endcase
384
end
385
 
386
assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i;
387
 
388
assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i;
389
 
390
`else
391
assign wb_rif_dat_i = wb_rim_dat_i;
392
assign wb_rif_ack_i = wb_rim_ack_i;
393
`endif
394
 
395
 
396
//
397
// TAP<->dbg_interface
398
//      
399
wire jtag_tck;
400
wire debug_tdi;
401
wire debug_tdo;
402
wire capture_dr;
403
wire shift_dr;
404
wire pause_dr;
405
wire update_dr;
406
 
407
wire debug_select;
408
wire test_logic_reset;
409
 
410
//
411
// Instantiation of the development i/f
412
//
413
adbg_top dbg_top  (
414
 
415
        // JTAG pins
416
      .tck_i    ( jtag_tck ),
417
      .tdi_i    ( debug_tdi ),
418
      .tdo_o    ( debug_tdo ),
419
      .rst_i    ( test_logic_reset ),           //cable without rst
420
 
421
        // Boundary Scan signals
422
      .capture_dr_i ( capture_dr ),
423
      .shift_dr_i  ( shift_dr ),
424
      .pause_dr_i  ( pause_dr ),
425
      .update_dr_i ( update_dr ),
426
 
427
      .debug_select_i( debug_select ),
428
        // WISHBONE common
429
      .wb_clk_i   ( wb_clk ),
430 156 nyawn
      .wb_rst_i   ( wb_rst ),
431 2 rfajardo
 
432
      // WISHBONE master interface
433
      .wb_adr_o  ( wb_dm_adr_o ),
434
      .wb_dat_i  ( wb_dm_dat_i ),
435
      .wb_dat_o  ( wb_dm_dat_o ),
436
      .wb_sel_o  ( wb_dm_sel_o ),
437
      .wb_we_o   ( wb_dm_we_o  ),
438
      .wb_stb_o  ( wb_dm_stb_o ),
439
      .wb_cyc_o  ( wb_dm_cyc_o ),
440
      .wb_ack_i  ( wb_dm_ack_i ),
441
      .wb_err_i  ( wb_dm_err_i ),
442
      .wb_cti_o  ( ),
443
      .wb_bte_o  ( ),
444
 
445
      // RISC signals
446
      .cpu0_clk_i  ( wb_clk ),
447
      .cpu0_addr_o ( dbg_adr ),
448
      .cpu0_data_i ( dbg_dat_risc ),
449
      .cpu0_data_o ( dbg_dat_dbg ),
450 156 nyawn
      .cpu0_bp_i   ( (dbg_bp | (| dbg_wp[10:0])) ),
451 2 rfajardo
      .cpu0_stall_o( dbg_stall ),
452 20 rfajardo
      .cpu0_stb_o  ( dbg_stb ),
453
      .cpu0_we_o   ( dbg_we ),
454 2 rfajardo
      .cpu0_ack_i  ( dbg_ack ),
455 158 rfajardo
      .cpu0_rst_o  ( ),
456 2 rfajardo
 
457 158 rfajardo
      // WISHBONE slave interface (JTAG UART)
458
`ifdef JSP
459
      .wb_jsp_adr_i     ( wb_jsp_adr_i[31:0] ),
460
      .wb_jsp_dat_i     ( wb_jsp_dat_i[31:0] ),
461
      .wb_jsp_dat_o     ( wb_jsp_dat_o[31:0] ),
462
      .wb_jsp_we_i      ( wb_jsp_we_i ),
463
      .wb_jsp_stb_i     ( wb_jsp_stb_i ),
464
      .wb_jsp_cyc_i     ( wb_jsp_cyc_i ),
465
      .wb_jsp_ack_o     ( wb_jsp_ack_o ),
466
      .wb_jsp_sel_i     ( wb_jsp_sel_i[3:0] ),
467
      .wb_jsp_cab_i     ( 1'b0 ),
468
      .wb_jsp_cti_i     ( 3'b0 ),
469
      .wb_jsp_bte_i     ( 2'b0 ),
470
 
471
       // Interrupt request
472
      .int_o ( pic_ints[`APP_INT_JSP] )
473
`else
474
      .wb_jsp_adr_i     ( 32'h0000_0000 ),
475
      .wb_jsp_dat_i     ( 32'h0000_0000 ),
476
      .wb_jsp_dat_o     ( ),
477
      .wb_jsp_we_i      ( 1'b0 ),
478
      .wb_jsp_stb_i     ( 1'b0 ),
479
      .wb_jsp_cyc_i     ( 1'b0 ),
480
      .wb_jsp_ack_o     ( ),
481
      .wb_jsp_sel_i     ( 4'h0 ),
482
      .wb_jsp_cab_i     ( 1'b0 ),
483
      .wb_jsp_cti_i     ( 3'b0 ),
484
      .wb_jsp_bte_i     ( 2'b0 ),
485
 
486
       // Interrupt request
487
      .int_o ( )
488
`endif
489 2 rfajardo
);
490
 
491 158 rfajardo
`ifdef JSP
492
    assign wb_jsp_err_o = 1'b0;
493
`else
494
        assign wb_jsp_dat_o = 32'h0000_0000;
495
        assign wb_jsp_ack_o = 1'b0;
496
    assign wb_jsp_err_o = 1'b1;
497
        assign pic_ints[`APP_INT_JSP] = 1'b0;
498
`endif
499
 
500
 
501 2 rfajardo
//
502
// JTAG TAP controller instantiation
503
//
504
`ifdef GENERIC_TAP
505
tap_top tap_top(
506
         // JTAG pads
507
         .tms_pad_i(jtag_tms),
508
         .tck_pad_i(jtag_tck),
509
         .trstn_pad_i(rstn),
510
         .tdi_pad_i(jtag_tdi),
511
         .tdo_pad_o(jtag_tdo),
512
         .tdo_padoe_o( ),
513
 
514
         // TAP states
515
         .test_logic_reset_o( test_logic_reset ),
516
         .run_test_idle_o(),
517
         .shift_dr_o(shift_dr),
518
         .pause_dr_o(pause_dr),
519
         .update_dr_o(update_dr),
520
         .capture_dr_o(capture_dr),
521
 
522
         // Select signals for boundary scan or mbist
523
         .extest_select_o(),
524
         .sample_preload_select_o(),
525
         .mbist_select_o(),
526
         .debug_select_o(debug_select),
527
 
528
         // TDO signal that is connected to TDI of sub-modules.
529
         .tdi_o(debug_tdi),
530
 
531
         // TDI signals from sub-modules
532
         .debug_tdo_i(debug_tdo),    // from debug module
533
         .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
534
         .mbist_tdo_i(1'b0)     // from Mbist Chain
535
);
536
`elsif FPGA_TAP
537
`ifdef ALTERA_FPGA
538
altera_virtual_jtag tap_top(
539
        .tck_o(jtag_tck),
540 26 rfajardo
        .debug_tdo_i(debug_tdo),
541 2 rfajardo
        .tdi_o(debug_tdi),
542
        .test_logic_reset_o(test_logic_reset),
543
        .run_test_idle_o(),
544
        .shift_dr_o(shift_dr),
545
        .capture_dr_o(capture_dr),
546
        .pause_dr_o(pause_dr),
547
        .update_dr_o(update_dr),
548
        .debug_select_o(debug_select)
549
);
550
`elsif XILINX_FPGA
551
minsoc_xilinx_internal_jtag tap_top(
552
        .tck_o( jtag_tck ),
553
        .debug_tdo_i( debug_tdo ),
554
        .tdi_o( debug_tdi ),
555
 
556
        .test_logic_reset_o( test_logic_reset ),
557
        .run_test_idle_o( ),
558
 
559
        .shift_dr_o( shift_dr ),
560
        .capture_dr_o( capture_dr ),
561
        .pause_dr_o( pause_dr ),
562
        .update_dr_o( update_dr ),
563
        .debug_select_o( debug_select )
564
);
565
`endif // !FPGA_TAP
566
 
567
`endif // !GENERIC_TAP
568
 
569
//
570
// Instantiation of the OR1200 RISC
571
//
572
or1200_top or1200_top (
573
 
574
        // Common
575
        .rst_i          ( wb_rst ),
576
        .clk_i          ( wb_clk ),
577
`ifdef OR1200_CLMODE_1TO2
578
        .clmode_i       ( 2'b01 ),
579
`else
580
`ifdef OR1200_CLMODE_1TO4
581
        .clmode_i       ( 2'b11 ),
582
`else
583
        .clmode_i       ( 2'b00 ),
584
`endif
585
`endif
586
 
587
        // WISHBONE Instruction Master
588
        .iwb_clk_i      ( wb_clk ),
589
        .iwb_rst_i      ( wb_rst ),
590
        .iwb_cyc_o      ( wb_rim_cyc_o ),
591
        .iwb_adr_o      ( wb_rim_adr_o ),
592
        .iwb_dat_i      ( wb_rif_dat_i ),
593
        .iwb_dat_o      ( wb_rim_dat_o ),
594
        .iwb_sel_o      ( wb_rim_sel_o ),
595
        .iwb_ack_i      ( wb_rif_ack_i ),
596
        .iwb_err_i      ( wb_rim_err_i ),
597
        .iwb_rty_i      ( wb_rim_rty_i ),
598
        .iwb_we_o       ( wb_rim_we_o  ),
599
        .iwb_stb_o      ( wb_rim_stb_o ),
600
 
601
        // WISHBONE Data Master
602
        .dwb_clk_i      ( wb_clk ),
603
        .dwb_rst_i      ( wb_rst ),
604
        .dwb_cyc_o      ( wb_rdm_cyc_o ),
605
        .dwb_adr_o      ( wb_rdm_adr_o ),
606
        .dwb_dat_i      ( wb_rdm_dat_i ),
607
        .dwb_dat_o      ( wb_rdm_dat_o ),
608
        .dwb_sel_o      ( wb_rdm_sel_o ),
609
        .dwb_ack_i      ( wb_rdm_ack_i ),
610
        .dwb_err_i      ( wb_rdm_err_i ),
611
        .dwb_rty_i      ( wb_rdm_rty_i ),
612
        .dwb_we_o       ( wb_rdm_we_o  ),
613
        .dwb_stb_o      ( wb_rdm_stb_o ),
614
 
615
        // Debug
616
        .dbg_stall_i    ( dbg_stall ),
617
        .dbg_dat_i      ( dbg_dat_dbg ),
618
        .dbg_adr_i      ( dbg_adr ),
619
        .dbg_ewt_i      ( 1'b0 ),
620
        .dbg_lss_o      ( dbg_lss ),
621
        .dbg_is_o       ( dbg_is ),
622
        .dbg_wp_o       ( dbg_wp ),
623
        .dbg_bp_o       ( dbg_bp ),
624
        .dbg_dat_o      ( dbg_dat_risc ),
625
        .dbg_ack_o      ( dbg_ack ),
626 20 rfajardo
        .dbg_stb_i      ( dbg_stb ),
627
        .dbg_we_i       ( dbg_we ),
628 2 rfajardo
 
629
        // Power Management
630
        .pm_clksd_o     ( ),
631
        .pm_cpustall_i  ( 1'b0 ),
632
        .pm_dc_gate_o   ( ),
633
        .pm_ic_gate_o   ( ),
634
        .pm_dmmu_gate_o ( ),
635
        .pm_immu_gate_o ( ),
636
        .pm_tt_gate_o   ( ),
637
        .pm_cpu_gate_o  ( ),
638
        .pm_wakeup_o    ( ),
639
        .pm_lvolt_o     ( ),
640
 
641
        // Interrupts
642
        .pic_ints_i     ( pic_ints )
643
);
644
 
645
//
646
// Startup OR1k
647
//
648
`ifdef START_UP
649
OR1K_startup OR1K_startup0
650
(
651
    .wb_adr_i(wb_fs_adr_i[6:2]),
652
    .wb_stb_i(wb_fs_stb_i),
653
    .wb_cyc_i(wb_fs_cyc_i),
654
    .wb_dat_o(wb_fs_dat_o),
655
    .wb_ack_o(wb_fs_ack_o),
656
    .wb_clk(wb_clk),
657
    .wb_rst(wb_rst)
658
);
659
 
660
spi_flash_top #
661
(
662
   .divider(0),
663
   .divider_len(2)
664
)
665
spi_flash_top0
666
(
667
   .wb_clk_i(wb_clk),
668
   .wb_rst_i(wb_rst),
669
   .wb_adr_i(wb_sp_adr_i[4:2]),
670
   .wb_dat_i(wb_sp_dat_i),
671
   .wb_dat_o(wb_sp_dat_o),
672
   .wb_sel_i(wb_sp_sel_i),
673
   .wb_we_i(wb_sp_we_i),
674
   .wb_stb_i(wb_sp_stb_i),
675
   .wb_cyc_i(wb_sp_cyc_i),
676
   .wb_ack_o(wb_sp_ack_o),
677
 
678
   .mosi_pad_o(spi_flash_mosi),
679
   .miso_pad_i(spi_flash_miso),
680
   .sclk_pad_o(spi_flash_sclk),
681
   .ss_pad_o(spi_flash_ss)
682
);
683 158 rfajardo
 
684
assign wb_fs_err_o = 1'b0;
685
assign wb_sp_err_o = 1'b0;
686
 
687 2 rfajardo
`else
688
assign wb_fs_dat_o = 32'h0000_0000;
689
assign wb_fs_ack_o = 1'b0;
690 158 rfajardo
assign wb_fs_err_o = 1'b1;
691 2 rfajardo
assign wb_sp_dat_o = 32'h0000_0000;
692
assign wb_sp_ack_o = 1'b0;
693 158 rfajardo
assign wb_sp_err_o = 1'b1;
694 2 rfajardo
`endif
695
 
696
//
697
// Instantiation of the SRAM controller
698
//
699 60 rfajardo
`ifdef MEMORY_MODEL
700
minsoc_memory_model #
701
`else
702 2 rfajardo
minsoc_onchip_ram_top #
703 60 rfajardo
`endif
704 2 rfajardo
(
705
    .adr_width(`MEMORY_ADR_WIDTH)     //16 blocks of 2048 bytes memory 32768
706
)
707
onchip_ram_top (
708
 
709
        // WISHBONE common
710
        .wb_clk_i       ( wb_clk ),
711
        .wb_rst_i       ( wb_rst ),
712
 
713
        // WISHBONE slave
714
        .wb_dat_i       ( wb_ss_dat_i ),
715
        .wb_dat_o       ( wb_ss_dat_o ),
716
        .wb_adr_i       ( wb_ss_adr_i ),
717
        .wb_sel_i       ( wb_ss_sel_i ),
718
        .wb_we_i        ( wb_ss_we_i  ),
719
        .wb_cyc_i       ( wb_ss_cyc_i ),
720
        .wb_stb_i       ( wb_ss_stb_i ),
721
        .wb_ack_o       ( wb_ss_ack_o ),
722
        .wb_err_o       ( wb_ss_err_o )
723
);
724
 
725
//
726
// Instantiation of the UART16550
727
//
728
`ifdef UART
729
uart_top uart_top (
730
 
731
        // WISHBONE common
732
        .wb_clk_i       ( wb_clk ),
733
        .wb_rst_i       ( wb_rst ),
734
 
735
        // WISHBONE slave
736
        .wb_adr_i       ( wb_us_adr_i[4:0] ),
737
        .wb_dat_i       ( wb_us_dat_i ),
738
        .wb_dat_o       ( wb_us_dat_o ),
739
        .wb_we_i        ( wb_us_we_i  ),
740
        .wb_stb_i       ( wb_us_stb_i ),
741
        .wb_cyc_i       ( wb_us_cyc_i ),
742
        .wb_ack_o       ( wb_us_ack_o ),
743
        .wb_sel_i       ( wb_us_sel_i ),
744
 
745
        // Interrupt request
746
        .int_o          ( pic_ints[`APP_INT_UART] ),
747
 
748
        // UART signals
749
        // serial input/output
750
        .stx_pad_o      ( uart_stx ),
751
        .srx_pad_i      ( uart_srx ),
752
 
753
        // modem signals
754
        .rts_pad_o      ( ),
755
        .cts_pad_i      ( 1'b0 ),
756
        .dtr_pad_o      ( ),
757
        .dsr_pad_i      ( 1'b0 ),
758
        .ri_pad_i       ( 1'b0 ),
759
        .dcd_pad_i      ( 1'b0 )
760
);
761 158 rfajardo
 
762
assign wb_us_err_o = 1'b0;
763 2 rfajardo
`else
764
assign wb_us_dat_o = 32'h0000_0000;
765
assign wb_us_ack_o = 1'b0;
766 158 rfajardo
assign wb_us_err_o = 1'b1;
767 17 rfajardo
 
768 16 rfajardo
assign pic_ints[`APP_INT_UART] = 1'b0;
769 2 rfajardo
`endif
770
 
771
//
772
// Instantiation of the Ethernet 10/100 MAC
773
//
774
`ifdef ETHERNET
775 75 rfajardo
ethmac ethmac (
776 2 rfajardo
 
777
        // WISHBONE common
778
        .wb_clk_i       ( wb_clk ),
779
        .wb_rst_i       ( wb_rst ),
780
 
781
        // WISHBONE slave
782
        .wb_dat_i       ( wb_es_dat_i ),
783
        .wb_dat_o       ( wb_es_dat_o ),
784
        .wb_adr_i       ( wb_es_adr_i[11:2] ),
785
        .wb_sel_i       ( wb_es_sel_i ),
786
        .wb_we_i        ( wb_es_we_i  ),
787
        .wb_cyc_i       ( wb_es_cyc_i ),
788
        .wb_stb_i       ( wb_es_stb_i ),
789
        .wb_ack_o       ( wb_es_ack_o ),
790
        .wb_err_o       ( wb_es_err_o ),
791
 
792
        // WISHBONE master
793
        .m_wb_adr_o     ( wb_em_adr_o ),
794
        .m_wb_sel_o     ( wb_em_sel_o ),
795
        .m_wb_we_o      ( wb_em_we_o  ),
796
        .m_wb_dat_o     ( wb_em_dat_o ),
797
        .m_wb_dat_i     ( wb_em_dat_i ),
798
        .m_wb_cyc_o     ( wb_em_cyc_o ),
799
        .m_wb_stb_o     ( wb_em_stb_o ),
800
        .m_wb_ack_i     ( wb_em_ack_i ),
801
        .m_wb_err_i     ( wb_em_err_i ),
802
 
803
        // TX
804
        .mtx_clk_pad_i  ( eth_tx_clk ),
805
        .mtxd_pad_o     ( eth_txd ),
806
        .mtxen_pad_o    ( eth_tx_en ),
807
        .mtxerr_pad_o   ( eth_tx_er ),
808
 
809
        // RX
810
        .mrx_clk_pad_i  ( eth_rx_clk ),
811
        .mrxd_pad_i     ( eth_rxd ),
812
        .mrxdv_pad_i    ( eth_rx_dv ),
813
        .mrxerr_pad_i   ( eth_rx_er ),
814
        .mcoll_pad_i    ( eth_col ),
815
        .mcrs_pad_i     ( eth_crs ),
816
 
817
        // MIIM
818
        .mdc_pad_o      ( eth_mdc ),
819
        .md_pad_i       ( eth_mdio ),
820
        .md_pad_o       ( eth_mdo ),
821
        .md_padoe_o     ( eth_mdoe ),
822
 
823
        // Interrupt
824
        .int_o          ( pic_ints[`APP_INT_ETH] )
825
);
826
`else
827
assign wb_es_dat_o = 32'h0000_0000;
828
assign wb_es_ack_o = 1'b0;
829 158 rfajardo
assign wb_es_err_o = 1'b1;
830 2 rfajardo
 
831
assign wb_em_adr_o = 32'h0000_0000;
832
assign wb_em_sel_o = 4'h0;
833
assign wb_em_we_o = 1'b0;
834
assign wb_em_dat_o = 32'h0000_0000;
835
assign wb_em_cyc_o = 1'b0;
836
assign wb_em_stb_o = 1'b0;
837 17 rfajardo
 
838 16 rfajardo
assign pic_ints[`APP_INT_ETH] = 1'b0;
839 2 rfajardo
`endif
840
 
841
//
842
// Instantiation of the Traffic COP
843
//
844
minsoc_tc_top #(`APP_ADDR_DEC_W,
845
         `APP_ADDR_SRAM,
846
         `APP_ADDR_DEC_W,
847
         `APP_ADDR_FLASH,
848
         `APP_ADDR_DECP_W,
849
         `APP_ADDR_PERIP,
850
         `APP_ADDR_DEC_W,
851
         `APP_ADDR_SPI,
852
         `APP_ADDR_ETH,
853
         `APP_ADDR_AUDIO,
854 158 rfajardo
         `APP_ADDR_UART,
855 2 rfajardo
         `APP_ADDR_PS2,
856 158 rfajardo
         `APP_ADDR_JSP,
857 2 rfajardo
         `APP_ADDR_RES2
858
        ) tc_top (
859
 
860
        // WISHBONE common
861
        .wb_clk_i       ( wb_clk ),
862
        .wb_rst_i       ( wb_rst ),
863
 
864
        // WISHBONE Initiator 0
865
        .i0_wb_cyc_i    ( 1'b0 ),
866
        .i0_wb_stb_i    ( 1'b0 ),
867
        .i0_wb_adr_i    ( 32'h0000_0000 ),
868
        .i0_wb_sel_i    ( 4'b0000 ),
869
        .i0_wb_we_i     ( 1'b0 ),
870
        .i0_wb_dat_i    ( 32'h0000_0000 ),
871
        .i0_wb_dat_o    ( ),
872
        .i0_wb_ack_o    ( ),
873
        .i0_wb_err_o    ( ),
874
 
875
        // WISHBONE Initiator 1
876
        .i1_wb_cyc_i    ( wb_em_cyc_o ),
877
        .i1_wb_stb_i    ( wb_em_stb_o ),
878
        .i1_wb_adr_i    ( wb_em_adr_o ),
879
        .i1_wb_sel_i    ( wb_em_sel_o ),
880
        .i1_wb_we_i     ( wb_em_we_o  ),
881
        .i1_wb_dat_i    ( wb_em_dat_o ),
882
        .i1_wb_dat_o    ( wb_em_dat_i ),
883
        .i1_wb_ack_o    ( wb_em_ack_i ),
884
        .i1_wb_err_o    ( wb_em_err_i ),
885
 
886
        // WISHBONE Initiator 2
887
        .i2_wb_cyc_i    ( 1'b0 ),
888
        .i2_wb_stb_i    ( 1'b0 ),
889
        .i2_wb_adr_i    ( 32'h0000_0000 ),
890
        .i2_wb_sel_i    ( 4'b0000 ),
891
        .i2_wb_we_i     ( 1'b0 ),
892
        .i2_wb_dat_i    ( 32'h0000_0000 ),
893
        .i2_wb_dat_o    ( ),
894
        .i2_wb_ack_o    ( ),
895
        .i2_wb_err_o    ( ),
896
 
897
        // WISHBONE Initiator 3
898
        .i3_wb_cyc_i    ( wb_dm_cyc_o ),
899
        .i3_wb_stb_i    ( wb_dm_stb_o ),
900
        .i3_wb_adr_i    ( wb_dm_adr_o ),
901
        .i3_wb_sel_i    ( wb_dm_sel_o ),
902
        .i3_wb_we_i     ( wb_dm_we_o  ),
903
        .i3_wb_dat_i    ( wb_dm_dat_o ),
904
        .i3_wb_dat_o    ( wb_dm_dat_i ),
905
        .i3_wb_ack_o    ( wb_dm_ack_i ),
906
        .i3_wb_err_o    ( wb_dm_err_i ),
907
 
908
        // WISHBONE Initiator 4
909
        .i4_wb_cyc_i    ( wb_rdm_cyc_o ),
910
        .i4_wb_stb_i    ( wb_rdm_stb_o ),
911
        .i4_wb_adr_i    ( wb_rdm_adr_o ),
912
        .i4_wb_sel_i    ( wb_rdm_sel_o ),
913
        .i4_wb_we_i     ( wb_rdm_we_o  ),
914
        .i4_wb_dat_i    ( wb_rdm_dat_o ),
915
        .i4_wb_dat_o    ( wb_rdm_dat_i ),
916
        .i4_wb_ack_o    ( wb_rdm_ack_i ),
917
        .i4_wb_err_o    ( wb_rdm_err_i ),
918
 
919
        // WISHBONE Initiator 5
920
        .i5_wb_cyc_i    ( wb_rim_cyc_o ),
921
        .i5_wb_stb_i    ( wb_rim_stb_o ),
922
        .i5_wb_adr_i    ( wb_rim_adr_o ),
923
        .i5_wb_sel_i    ( wb_rim_sel_o ),
924
        .i5_wb_we_i     ( wb_rim_we_o  ),
925
        .i5_wb_dat_i    ( wb_rim_dat_o ),
926
        .i5_wb_dat_o    ( wb_rim_dat_i ),
927
        .i5_wb_ack_o    ( wb_rim_ack_i ),
928
        .i5_wb_err_o    ( wb_rim_err_i ),
929
 
930
        // WISHBONE Initiator 6
931
        .i6_wb_cyc_i    ( 1'b0 ),
932
        .i6_wb_stb_i    ( 1'b0 ),
933
        .i6_wb_adr_i    ( 32'h0000_0000 ),
934
        .i6_wb_sel_i    ( 4'b0000 ),
935
        .i6_wb_we_i     ( 1'b0 ),
936
        .i6_wb_dat_i    ( 32'h0000_0000 ),
937
        .i6_wb_dat_o    ( ),
938
        .i6_wb_ack_o    ( ),
939
        .i6_wb_err_o    ( ),
940
 
941
        // WISHBONE Initiator 7
942
        .i7_wb_cyc_i    ( 1'b0 ),
943
        .i7_wb_stb_i    ( 1'b0 ),
944
        .i7_wb_adr_i    ( 32'h0000_0000 ),
945
        .i7_wb_sel_i    ( 4'b0000 ),
946
        .i7_wb_we_i     ( 1'b0 ),
947
        .i7_wb_dat_i    ( 32'h0000_0000 ),
948
        .i7_wb_dat_o    ( ),
949
        .i7_wb_ack_o    ( ),
950
        .i7_wb_err_o    ( ),
951
 
952
        // WISHBONE Target 0
953
        .t0_wb_cyc_o    ( wb_ss_cyc_i ),
954
        .t0_wb_stb_o    ( wb_ss_stb_i ),
955
        .t0_wb_adr_o    ( wb_ss_adr_i ),
956
        .t0_wb_sel_o    ( wb_ss_sel_i ),
957
        .t0_wb_we_o     ( wb_ss_we_i  ),
958
        .t0_wb_dat_o    ( wb_ss_dat_i ),
959
        .t0_wb_dat_i    ( wb_ss_dat_o ),
960
        .t0_wb_ack_i    ( wb_ss_ack_o ),
961
        .t0_wb_err_i    ( wb_ss_err_o ),
962
 
963
        // WISHBONE Target 1
964
        .t1_wb_cyc_o    ( wb_fs_cyc_i ),
965
        .t1_wb_stb_o    ( wb_fs_stb_i ),
966
        .t1_wb_adr_o    ( wb_fs_adr_i ),
967
        .t1_wb_sel_o    ( wb_fs_sel_i ),
968
        .t1_wb_we_o     ( wb_fs_we_i  ),
969
        .t1_wb_dat_o    ( wb_fs_dat_i ),
970
        .t1_wb_dat_i    ( wb_fs_dat_o ),
971
        .t1_wb_ack_i    ( wb_fs_ack_o ),
972
        .t1_wb_err_i    ( wb_fs_err_o ),
973
 
974
        // WISHBONE Target 2
975
        .t2_wb_cyc_o    ( wb_sp_cyc_i ),
976
        .t2_wb_stb_o    ( wb_sp_stb_i ),
977
        .t2_wb_adr_o    ( wb_sp_adr_i ),
978
        .t2_wb_sel_o    ( wb_sp_sel_i ),
979
        .t2_wb_we_o     ( wb_sp_we_i  ),
980
        .t2_wb_dat_o    ( wb_sp_dat_i ),
981
        .t2_wb_dat_i    ( wb_sp_dat_o ),
982
        .t2_wb_ack_i    ( wb_sp_ack_o ),
983
        .t2_wb_err_i    ( wb_sp_err_o ),
984
 
985
        // WISHBONE Target 3
986
        .t3_wb_cyc_o    ( wb_es_cyc_i ),
987
        .t3_wb_stb_o    ( wb_es_stb_i ),
988
        .t3_wb_adr_o    ( wb_es_adr_i ),
989
        .t3_wb_sel_o    ( wb_es_sel_i ),
990
        .t3_wb_we_o     ( wb_es_we_i  ),
991
        .t3_wb_dat_o    ( wb_es_dat_i ),
992
        .t3_wb_dat_i    ( wb_es_dat_o ),
993
        .t3_wb_ack_i    ( wb_es_ack_o ),
994
        .t3_wb_err_i    ( wb_es_err_o ),
995
 
996
        // WISHBONE Target 4
997
        .t4_wb_cyc_o    ( ),
998
        .t4_wb_stb_o    ( ),
999
        .t4_wb_adr_o    ( ),
1000
        .t4_wb_sel_o    ( ),
1001
        .t4_wb_we_o     ( ),
1002
        .t4_wb_dat_o    ( ),
1003
        .t4_wb_dat_i    ( 32'h0000_0000 ),
1004
        .t4_wb_ack_i    ( 1'b0 ),
1005
        .t4_wb_err_i    ( 1'b1 ),
1006
 
1007
        // WISHBONE Target 5
1008
        .t5_wb_cyc_o    ( wb_us_cyc_i ),
1009
        .t5_wb_stb_o    ( wb_us_stb_i ),
1010
        .t5_wb_adr_o    ( wb_us_adr_i ),
1011
        .t5_wb_sel_o    ( wb_us_sel_i ),
1012
        .t5_wb_we_o     ( wb_us_we_i  ),
1013
        .t5_wb_dat_o    ( wb_us_dat_i ),
1014
        .t5_wb_dat_i    ( wb_us_dat_o ),
1015
        .t5_wb_ack_i    ( wb_us_ack_o ),
1016 158 rfajardo
    .t5_wb_err_i        ( wb_us_err_o ),
1017
 
1018 2 rfajardo
        // WISHBONE Target 6
1019
        .t6_wb_cyc_o    ( ),
1020
        .t6_wb_stb_o    ( ),
1021
        .t6_wb_adr_o    ( ),
1022
        .t6_wb_sel_o    ( ),
1023
        .t6_wb_we_o     ( ),
1024
        .t6_wb_dat_o    ( ),
1025
        .t6_wb_dat_i    ( 32'h0000_0000 ),
1026
        .t6_wb_ack_i    ( 1'b0 ),
1027
        .t6_wb_err_i    ( 1'b1 ),
1028
 
1029
        // WISHBONE Target 7
1030 158 rfajardo
    .t7_wb_cyc_o        ( wb_jsp_cyc_i ),
1031
    .t7_wb_stb_o        ( wb_jsp_stb_i ),
1032
    .t7_wb_adr_o        ( wb_jsp_adr_i ),
1033
    .t7_wb_sel_o        ( wb_jsp_sel_i ),
1034
    .t7_wb_we_o ( wb_jsp_we_i  ),
1035
    .t7_wb_dat_o        ( wb_jsp_dat_i ),
1036
    .t7_wb_dat_i        ( wb_jsp_dat_o ),
1037
    .t7_wb_ack_i        ( wb_jsp_ack_o ),
1038
    .t7_wb_err_i        ( wb_jsp_err_o ),
1039 2 rfajardo
 
1040 158 rfajardo
    // WISHBONE Target 8
1041 2 rfajardo
        .t8_wb_cyc_o    ( ),
1042
        .t8_wb_stb_o    ( ),
1043
        .t8_wb_adr_o    ( ),
1044
        .t8_wb_sel_o    ( ),
1045
        .t8_wb_we_o     ( ),
1046
        .t8_wb_dat_o    ( ),
1047
        .t8_wb_dat_i    ( 32'h0000_0000 ),
1048
        .t8_wb_ack_i    ( 1'b0 ),
1049
        .t8_wb_err_i    ( 1'b1 )
1050
);
1051
 
1052
//initial begin
1053
//  $dumpvars(0);
1054
//  $dumpfile("dump.vcd");
1055
//end
1056
 
1057
endmodule

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