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[/] [minsoc/] [trunk/] [sw/] [support/] [or1200.h] - Blame information for rev 141

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1 54 ConX.
/* or1200.h -- Defines OR1K architecture specific special-purpose registers
2
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3
 
4
   This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
/* This file is also used by microkernel test bench. Among
21
   others it is also used in assembly file(s). */
22
 
23 74 rfajardo
#define __CLABEL(prefix, label) prefix ## label
24
#define _CLABEL(prefix, label) __CLABEL(prefix, label)
25
#define CLABEL(label) _CLABEL(__USER_LABEL_PREFIX__, label)
26
 
27 54 ConX.
/* Definition of special-purpose registers (SPRs) */
28
 
29
#define MAX_GRPS (32)
30
#define MAX_SPRS_PER_GRP_BITS (11)
31
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
32
#define MAX_SPRS (0x10000)
33
 
34
/* Base addresses for the groups */
35
#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)
36
#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)
37
#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)
38
#define SPRGROUP_DC     (3<< MAX_SPRS_PER_GRP_BITS)
39
#define SPRGROUP_IC     (4<< MAX_SPRS_PER_GRP_BITS)
40
#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)
41
#define SPRGROUP_D      (6<< MAX_SPRS_PER_GRP_BITS)
42
#define SPRGROUP_PC     (7<< MAX_SPRS_PER_GRP_BITS)
43
#define SPRGROUP_PM     (8<< MAX_SPRS_PER_GRP_BITS)
44
#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)
45
#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
46
 
47
/* System control and status group */
48
#define SPR_VR          (SPRGROUP_SYS + 0)
49
#define SPR_UPR         (SPRGROUP_SYS + 1)
50
#define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
51
#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
52
#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
53
#define SPR_DCCFGR      (SPRGROUP_SYS + 5)
54
#define SPR_ICCFGR      (SPRGROUP_SYS + 6)
55
#define SPR_DCFGR       (SPRGROUP_SYS + 7)
56
#define SPR_PCCFGR      (SPRGROUP_SYS + 8)
57
#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
58
#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
59
#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
60
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
61
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
62
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
63
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
64
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
65
#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
66
 
67
#if 0
68
/* Data MMU group */
69
#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
70
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
71
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
72
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
73
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
74
 
75
/* Instruction MMU group */
76
#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
77
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
78
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
79
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
80
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
81
#else
82
 
83
/* Data MMU group */
84
#define SPR_DMMUCR  (SPRGROUP_DMMU + 0)
85
#define SPR_DTLBMR_BASE(WAY)  (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
86
#define SPR_DTLBMR_LAST(WAY)  (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
87
#define SPR_DTLBTR_BASE(WAY)  (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
88
#define SPR_DTLBTR_LAST(WAY)  (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
89
 
90
/* Instruction MMU group */
91
#define SPR_IMMUCR  (SPRGROUP_IMMU + 0)
92
#define SPR_ITLBMR_BASE(WAY)  (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
93
#define SPR_ITLBMR_LAST(WAY)  (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
94
#define SPR_ITLBTR_BASE(WAY)  (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
95
#define SPR_ITLBTR_LAST(WAY)  (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
96
#endif
97
/* Data cache group */
98
#define SPR_DCCR        (SPRGROUP_DC + 0)
99
#define SPR_DCBPR       (SPRGROUP_DC + 1)
100
#define SPR_DCBFR       (SPRGROUP_DC + 2)
101
#define SPR_DCBIR       (SPRGROUP_DC + 3)
102
#define SPR_DCBWR       (SPRGROUP_DC + 4)
103
#define SPR_DCBLR       (SPRGROUP_DC + 5)
104
#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
105
#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
106
 
107
/* Instruction cache group */
108
#define SPR_ICCR        (SPRGROUP_IC + 0)
109
#define SPR_ICBPR       (SPRGROUP_IC + 1)
110
#define SPR_ICBIR       (SPRGROUP_IC + 2)
111
#define SPR_ICBLR       (SPRGROUP_IC + 3)
112
#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
113
#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
114
 
115
/* MAC group */
116
#define SPR_MACLO       (SPRGROUP_MAC + 1)
117
#define SPR_MACHI       (SPRGROUP_MAC + 2)
118
 
119
/* Debug group */
120
#define SPR_DVR(N)      (SPRGROUP_D + (N))
121
#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
122
#define SPR_DMR1        (SPRGROUP_D + 16)
123
#define SPR_DMR2        (SPRGROUP_D + 17)
124
#define SPR_DWCR0       (SPRGROUP_D + 18)
125
#define SPR_DWCR1       (SPRGROUP_D + 19)
126
#define SPR_DSR         (SPRGROUP_D + 20)
127
#define SPR_DRR         (SPRGROUP_D + 21)
128
 
129
/* Performance counters group */
130
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
131
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
132
 
133
/* Power management group */
134
#define SPR_PMR (SPRGROUP_PM + 0)
135
 
136
/* PIC group */
137
#define SPR_PICMR (SPRGROUP_PIC + 0)
138
#define SPR_PICPR (SPRGROUP_PIC + 1)
139
#define SPR_PICSR (SPRGROUP_PIC + 2)
140
 
141
/* Tick Timer group */
142
#define SPR_TTMR (SPRGROUP_TT + 0)
143
#define SPR_TTCR (SPRGROUP_TT + 1)
144
 
145
/*
146
 * Bit definitions for the Version Register
147
 *
148
 */
149
#define SPR_VR_VER      0xffff0000  /* Processor version */
150
#define SPR_VR_REV      0x0000003f  /* Processor revision */
151
 
152
/*
153
 * Bit definitions for the Unit Present Register
154
 *
155
 */
156
#define SPR_UPR_UP      0x00000001  /* UPR present */
157
#define SPR_UPR_DCP     0x00000002  /* Data cache present */
158
#define SPR_UPR_ICP     0x00000004  /* Instruction cache present */
159
#define SPR_UPR_DMP     0x00000008  /* Data MMU present */
160
#define SPR_UPR_IMP     0x00000010  /* Instruction MMU present */
161
#define SPR_UPR_OB32P   0x00000020  /* ORBIS32 present */
162
#define SPR_UPR_OB64P   0x00000040  /* ORBIS64 present */
163
#define SPR_UPR_OF32P   0x00000080  /* ORFPX32 present */
164
#define SPR_UPR_OF64P   0x00000100  /* ORFPX64 present */
165
#define SPR_UPR_OV32P   0x00000200  /* ORVDX32 present */
166
#define SPR_UPR_OV64P   0x00000400  /* ORVDX64 present */
167
#define SPR_UPR_DUP     0x00000800  /* Debug unit present */
168
#define SPR_UPR_PCUP    0x00001000  /* Performance counters unit present */
169
#define SPR_UPR_PMP     0x00002000  /* Power management present */
170
#define SPR_UPR_PICP    0x00004000  /* PIC present */
171
#define SPR_UPR_TTP     0x00008000  /* Tick timer present */
172
#define SPR_UPR_SRP     0x00010000  /* Shadow registers present */
173
#define SPR_UPR_RES     0x00fe0000  /* ORVDX32 present */
174
#define SPR_UPR_CUST    0xff000000  /* Custom units */
175
 
176
/*
177
 * Bit definitions for the Supervision Register
178
 *
179
 */
180
#define SPR_SR_CID      0xf0000000  /* Context ID */
181
#define SPR_SR_FO       0x00008000  /* Fixed one */
182
#define SPR_SR_EPH      0x00004000  /* Exception Prefixi High */
183
#define SPR_SR_DSX      0x00002000  /* Delay Slot Exception */
184
#define SPR_SR_OVE      0x00001000  /* Overflow flag Exception */
185
#define SPR_SR_OV       0x00000800  /* Overflow flag */
186
#define SPR_SR_CY       0x00000400  /* Carry flag */
187
#define SPR_SR_F        0x00000200  /* Condition Flag */
188
#define SPR_SR_CE       0x00000100  /* CID Enable */
189
#define SPR_SR_LEE      0x00000080  /* Little Endian Enable */
190
#define SPR_SR_IME      0x00000040  /* Instruction MMU Enable */
191
#define SPR_SR_DME      0x00000020  /* Data MMU Enable */
192
#define SPR_SR_ICE      0x00000010  /* Instruction Cache Enable */
193
#define SPR_SR_DCE      0x00000008  /* Data Cache Enable */
194
#define SPR_SR_IEE      0x00000004  /* Interrupt Exception Enable */
195
#define SPR_SR_TEE      0x00000002  /* Tick timer Exception Enable */
196
#define SPR_SR_SM       0x00000001  /* Supervisor Mode */
197
 
198
/*
199
 * Bit definitions for the Data MMU Control Register
200
 *
201
 */
202
#define SPR_DMMUCR_P2S  0x0000003e  /* Level 2 Page Size */
203
#define SPR_DMMUCR_P1S  0x000007c0  /* Level 1 Page Size */
204
#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
205
#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
206
 
207
/*
208
 * Bit definitions for the Instruction MMU Control Register
209
 *
210
 */
211
#define SPR_IMMUCR_P2S  0x0000003e  /* Level 2 Page Size */
212
#define SPR_IMMUCR_P1S  0x000007c0  /* Level 1 Page Size */
213
#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
214
#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
215
 
216
/*
217
 * Bit definitions for the Data TLB Match Register
218
 *
219
 */
220
#define SPR_DTLBMR_V    0x00000001  /* Valid */
221
#define SPR_DTLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */
222
#define SPR_DTLBMR_CID  0x0000003c  /* Context ID */
223
#define SPR_DTLBMR_LRU  0x000000c0  /* Least Recently Used */
224
#define SPR_DTLBMR_VPN  0xfffff000  /* Virtual Page Number */
225
 
226
/*
227
 * Bit definitions for the Data TLB Translate Register
228
 *
229
 */
230
#define SPR_DTLBTR_CC   0x00000001  /* Cache Coherency */
231
#define SPR_DTLBTR_CI   0x00000002  /* Cache Inhibit */
232
#define SPR_DTLBTR_WBC  0x00000004  /* Write-Back Cache */
233
#define SPR_DTLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
234
#define SPR_DTLBTR_A    0x00000010  /* Accessed */
235
#define SPR_DTLBTR_D    0x00000020  /* Dirty */
236
#define SPR_DTLBTR_URE  0x00000040  /* User Read Enable */
237
#define SPR_DTLBTR_UWE  0x00000080  /* User Write Enable */
238
#define SPR_DTLBTR_SRE  0x00000100  /* Supervisor Read Enable */
239
#define SPR_DTLBTR_SWE  0x00000200  /* Supervisor Write Enable */
240
#define SPR_DTLBTR_PPN  0xfffff000  /* Physical Page Number */
241
#define DTLB_PR_NOLIMIT  (SPR_DTLBTR_URE  | \
242
                SPR_DTLBTR_UWE  | \
243
                SPR_DTLBTR_SRE  | \
244
                SPR_DTLBTR_SWE  )
245
/*
246
 * Bit definitions for the Instruction TLB Match Register
247
 *
248
 */
249
#define SPR_ITLBMR_V    0x00000001  /* Valid */
250
#define SPR_ITLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */
251
#define SPR_ITLBMR_CID  0x0000003c  /* Context ID */
252
#define SPR_ITLBMR_LRU  0x000000c0  /* Least Recently Used */
253
#define SPR_ITLBMR_VPN  0xfffff000  /* Virtual Page Number */
254
 
255
/*
256
 * Bit definitions for the Instruction TLB Translate Register
257
 *
258
 */
259
#define SPR_ITLBTR_CC   0x00000001  /* Cache Coherency */
260
#define SPR_ITLBTR_CI   0x00000002  /* Cache Inhibit */
261
#define SPR_ITLBTR_WBC  0x00000004  /* Write-Back Cache */
262
#define SPR_ITLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
263
#define SPR_ITLBTR_A    0x00000010  /* Accessed */
264
#define SPR_ITLBTR_D    0x00000020  /* Dirty */
265
#define SPR_ITLBTR_SXE  0x00000040  /* User Read Enable */
266
#define SPR_ITLBTR_UXE  0x00000080  /* User Write Enable */
267
#define SPR_ITLBTR_PPN  0xfffff000  /* Physical Page Number */
268
#define ITLB_PR_NOLIMIT  (SPR_ITLBTR_SXE  | \
269
                SPR_ITLBTR_UXE  )
270
 
271
 
272
/*
273
 * Bit definitions for Data Cache Control register
274
 *
275
 */
276
#define SPR_DCCR_EW     0x000000ff  /* Enable ways */
277
 
278
/*
279
 * Bit definitions for Insn Cache Control register
280
 *
281
 */
282
#define SPR_ICCR_EW     0x000000ff  /* Enable ways */
283
 
284
/*
285
 * Bit definitions for Debug Control registers
286
 *
287
 */
288
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
289
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
290
#define SPR_DCR_SC      0x00000010  /* Signed compare */
291
#define SPR_DCR_CT      0x000000e0  /* Compare to */
292
 
293
/* Bit results with SPR_DCR_CC mask */
294
#define SPR_DCR_CC_MASKED 0x00000000
295
#define SPR_DCR_CC_EQUAL  0x00000001
296
#define SPR_DCR_CC_LESS   0x00000002
297
#define SPR_DCR_CC_LESSE  0x00000003
298
#define SPR_DCR_CC_GREAT  0x00000004
299
#define SPR_DCR_CC_GREATE 0x00000005
300
#define SPR_DCR_CC_NEQUAL 0x00000006
301
 
302
/* Bit results with SPR_DCR_CT mask */
303
#define SPR_DCR_CT_DISABLED 0x00000000
304
#define SPR_DCR_CT_IFEA     0x00000020
305
#define SPR_DCR_CT_LEA      0x00000040
306
#define SPR_DCR_CT_SEA      0x00000060
307
#define SPR_DCR_CT_LD       0x00000080
308
#define SPR_DCR_CT_SD       0x000000a0
309
#define SPR_DCR_CT_LSEA     0x000000c0
310
 
311
/*
312
 * Bit definitions for Debug Mode 1 register
313
 *
314
 */
315
#define SPR_DMR1_CW0    0x00000003  /* Chain watchpoint 0 */
316
#define SPR_DMR1_CW1    0x0000000c  /* Chain watchpoint 1 */
317
#define SPR_DMR1_CW2    0x00000030  /* Chain watchpoint 2 */
318
#define SPR_DMR1_CW3    0x000000c0  /* Chain watchpoint 3 */
319
#define SPR_DMR1_CW4    0x00000300  /* Chain watchpoint 4 */
320
#define SPR_DMR1_CW5    0x00000c00  /* Chain watchpoint 5 */
321
#define SPR_DMR1_CW6    0x00003000  /* Chain watchpoint 6 */
322
#define SPR_DMR1_CW7    0x0000c000  /* Chain watchpoint 7 */
323
#define SPR_DMR1_CW8    0x00030000  /* Chain watchpoint 8 */
324
#define SPR_DMR1_CW9    0x000c0000  /* Chain watchpoint 9 */
325
#define SPR_DMR1_CW10   0x00300000  /* Chain watchpoint 10 */
326
#define SPR_DMR1_ST     0x00400000  /* Single-step trace*/
327
#define SPR_DMR1_BT     0x00800000  /* Branch trace */
328
#define SPR_DMR1_DXFW   0x01000000  /* Disable external force watchpoint */
329
 
330
/*
331
 * Bit definitions for Debug Mode 2 register
332
 *
333
 */
334
#define SPR_DMR2_WCE0   0x00000001  /* Watchpoint counter 0 enable */
335
#define SPR_DMR2_WCE1   0x00000002  /* Watchpoint counter 0 enable */
336
#define SPR_DMR2_AWTC   0x00001ffc  /* Assign watchpoints to counters */
337
#define SPR_DMR2_WGB    0x00ffe000  /* Watchpoints generating breakpoint */
338
 
339
/*
340
 * Bit definitions for Debug watchpoint counter registers
341
 *
342
 */
343
#define SPR_DWCR_COUNT  0x0000ffff  /* Count */
344
#define SPR_DWCR_MATCH  0xffff0000  /* Match */
345
 
346
/*
347
 * Bit definitions for Debug stop register
348
 *
349
 */
350
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
351
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
352
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
353
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
354
#define SPR_DSR_TTE     0x00000010  /* iTick Timer exception */
355
#define SPR_DSR_AE      0x00000020  /* Alignment exception */
356
#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
357
#define SPR_DSR_IE      0x00000080  /* Interrupt exception */
358
#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
359
#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
360
#define SPR_DSR_RE      0x00000400  /* Range exception */
361
#define SPR_DSR_SCE     0x00000800  /* System call exception */
362
#define SPR_DSR_SSE     0x00001000  /* Single Step Exception */
363
#define SPR_DSR_TE      0x00002000  /* Trap exception */
364
 
365
/*
366
 * Bit definitions for Debug reason register
367
 *
368
 */
369
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
370
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
371
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
372
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
373
#define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
374
#define SPR_DRR_AE      0x00000020  /* Alignment exception */
375
#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
376
#define SPR_DRR_IE      0x00000080  /* Interrupt exception */
377
#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
378
#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
379
#define SPR_DRR_RE      0x00000400  /* Range exception */
380
#define SPR_DRR_SCE     0x00000800  /* System call exception */
381
#define SPR_DRR_TE      0x00001000  /* Trap exception */
382
 
383
/*
384
 * Bit definitions for Performance counters mode registers
385
 *
386
 */
387
#define SPR_PCMR_CP     0x00000001  /* Counter present */
388
#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
389
#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
390
#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
391
#define SPR_PCMR_LA     0x00000010  /* Load access event */
392
#define SPR_PCMR_SA     0x00000020  /* Store access event */
393
#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
394
#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
395
#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
396
#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
397
#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
398
#define SPR_PCMR_BS     0x00000800  /* Branch stall event */
399
#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
400
#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
401
#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
402
#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
403
 
404
/*
405
 * Bit definitions for the Power management register
406
 *
407
 */
408
#define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
409
#define SPR_PMR_DME     0x00000010  /* Doze mode enable */
410
#define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
411
#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
412
#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
413
 
414
/*
415
 * Bit definitions for PICMR
416
 *
417
 */
418
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
419
 
420
/*
421
 * Bit definitions for PICPR
422
 *
423
 */
424
#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
425
 
426
/*
427
 * Bit definitions for PICSR
428
 *
429
 */
430
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
431
 
432
/*
433
 * Bit definitions for Tick Timer Control Register
434
 *
435
 */
436
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
437
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
438
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
439
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
440
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
441
#define SPR_TTMR_SR     0x80000000  /* Single run */
442
#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
443
#define SPR_TTMR_M      0xc0000000  /* Tick mode */
444
 
445
/*
446
 * l.nop constants
447
 *
448
 */
449
#define NOP_NOP         0x0000      /* Normal nop instruction */
450
#define NOP_EXIT        0x0001      /* End of simulation */
451
#define NOP_REPORT      0x0002      /* Simple report */
452
#define NOP_PRINTF      0x0003      /* Simprintf instruction */
453
#define NOP_REPORT_FIRST 0x0400     /* Report with number */
454
#define NOP_REPORT_LAST 0x03ff      /* Report with number */

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