OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [syn/] [xilinx/] [Makefile] - Blame information for rev 88

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 64 rfajardo
MINSOC = ../
2
MINSOC_DEFINES = ${MINSOC}/backend
3
MINSOC_RTL = ${MINSOC}/rtl/verilog
4
MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup
5
UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog
6
ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware
7
DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog
8
OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog
9
ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog
10 85 rfajardo
BUILD_SUPPORT = $(MINSOC)/syn/buildSupport
11 88 rfajardo
PROJECT_DIR = $(MINSOC)/prj/xilinx
12 63 rfajardo
 
13
help:
14
        @echo "  all: Synthesize and implement the SoC, then generate a bit stream"
15 64 rfajardo
        @echo ""
16 63 rfajardo
        @echo "  soc: Synthesize the SoC"
17
        @echo "  translate: Convert the SoC's ngc file to an ngd file for mapping"
18
        @echo "  map: Express the SoC netlist in the target hardware"
19
        @echo "  par: Place the target hardware, then route the wires"
20
        @echo "  bitgen: Generate a programming file for the target FPGA"
21 64 rfajardo
        @echo ""
22
        @echo "  modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers"
23 63 rfajardo
        @echo "  or1200: Synthesize the OR1200 processor"
24
        @echo "  debug: Synthesize the debug interface"
25
        @echo "  uart: Synthesize the UART"
26 64 rfajardo
        @echo "  eth: Synthesize the Ethernet controller"
27
        @echo ""
28
        @echo "  clean: Delete all superfluous files generated by Xilinx tools"
29
        @echo "  distclean: Delete all generated files"
30 63 rfajardo
 
31 64 rfajardo
all: minsoc.bit
32 63 rfajardo
soc: minsoc_top.ngc
33
translate: minsoc.ngd
34
map: minsoc.ncd
35
par: minsoc_par.ncd
36
bitgen: minsoc.bit
37 64 rfajardo
modules: or1200 debug uart eth
38 85 rfajardo
MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc ethmac.ngc
39 63 rfajardo
 
40 64 rfajardo
prepare:
41
        rm -rf xst
42
        mkdir xst
43
clean:
44
        rm -rf _xmsgs xst xlnx_auto_0_xdb
45 73 rfajardo
        rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html
46 63 rfajardo
distclean:
47 64 rfajardo
        rm -rf *.ngc *.ncd *.ngd *.bit
48
        make clean
49 63 rfajardo
 
50 88 rfajardo
minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.xst $(PROJECT_DIR)/minsoc_top.prj
51 64 rfajardo
        make prepare
52 85 rfajardo
        xst -ifn "$(BUILD_SUPPORT)/minsoc_top.xst"
53 63 rfajardo
 
54
uart: uart_top.ngc
55 88 rfajardo
uart_top.ngc: ${UART_RTL}/*.v $(BUILD_SUPPORT)/uart_top.xst $(PROJECT_DIR)/uart_top.prj
56 64 rfajardo
        make prepare
57 85 rfajardo
        xst -ifn "$(BUILD_SUPPORT)/uart_top.xst"
58 63 rfajardo
 
59 85 rfajardo
eth: ethmac.ngc
60 88 rfajardo
ethmac.ngc: ${ETH_RTL}/*.v $(BUILD_SUPPORT)/ethmac.xst $(PROJECT_DIR)/ethmac.prj
61 64 rfajardo
        make prepare
62 85 rfajardo
        xst -ifn "$(BUILD_SUPPORT)/ethmac.xst"
63 63 rfajardo
 
64
debug: adbg_top.ngc
65 88 rfajardo
adbg_top.ngc: ${DEBUG_RTL}/*.v $(BUILD_SUPPORT)/adbg_top.xst $(PROJECT_DIR)/adbg_top.prj
66 64 rfajardo
        make prepare
67 85 rfajardo
        xst -ifn "$(BUILD_SUPPORT)/adbg_top.xst"
68 63 rfajardo
 
69
or1200: or1200_top.ngc
70 88 rfajardo
or1200_top.ngc: ${OR1200_RTL}/*.v $(BUILD_SUPPORT)/or1200_top.xst $(PROJECT_DIR)/or1200_top.prj
71 64 rfajardo
        make prepare
72 85 rfajardo
        xst -ifn "$(BUILD_SUPPORT)/or1200_top.xst"
73 63 rfajardo
 
74 64 rfajardo
minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES)
75
        ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd
76 63 rfajardo
 
77 64 rfajardo
minsoc.ncd: minsoc.ngd
78 63 rfajardo
        map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd
79
 
80
minsoc_par.ncd: minsoc.ncd
81
        par -ol high -w -xe n minsoc.ncd minsoc_par.ncd
82
 
83
minsoc.bit: minsoc_par.ncd
84
        bitgen -d -w minsoc_par.ncd minsoc.bit

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.